Digital Implementation

Latest Posts

Discussion

The viaGen found no shadow vias to rebuild

Category: Digital Implementation

By archive
•
updated over 17 years ago by Renee

2 replies • 13110 views
Discussion

Xilinx xc9500 and orcad 10.5

Category: Digital Implementation

By jyoung
•
started over 17 years ago

0 replies • 12687 views
Discussion

How to connect endcap cell vertically in soc encounter?

Category: Digital Implementation

By Renee
•
updated over 17 years ago by Kari

10 replies • 15792 views
Discussion

replace library cells

Category: Digital Implementation

By designer
•
updated over 17 years ago by designer

2 replies • 13240 views
Discussion

error after CTS: ERROR:TCLCMD-917

Category: Digital Implementation

By kulprashant
•
updated over 17 years ago by kulprashant

10 replies • 5415 views
Discussion

Why encounter places std cells on macro?

Category: Digital Implementation

By archive
•
updated over 17 years ago by ScreenName

1 replies • 13100 views
Discussion

How to set global clock signal routing in soc encounter?

Category: Digital Implementation

By Renee
•
updated over 17 years ago by Kari

1 replies • 13046 views
Discussion

senthesize sub-module

Category: Digital Implementation

By designer
•
started over 17 years ago

0 replies • 12822 views
Discussion

soc encounter output to Magic

Category: Digital Implementation

By Renee
•
updated over 17 years ago by Renee

4 replies • 13509 views
Discussion

First Encounter pin placement/layer

Category: Digital Implementation

By archive
•
updated over 17 years ago by Kari

9 replies • 7934 views
Discussion

Number of Non Equivalence Points after comparison in LEC Conformal

Category: Digital Implementation

By Azhar
•
updated over 17 years ago by Azhar

1 replies • 14676 views
Discussion

Encounter/Nanoroute - fixing DRC violations while keeping critical pre-routes untouched

Category: Digital Implementation

By ccabal
•
updated over 17 years ago by ccabal

4 replies • 5293 views
Discussion

Disable clock gating check for a module.

Category: Digital Implementation

By Tongju
•
started over 17 years ago

0 replies • 15538 views
Discussion

How to stream in Verilog to Virtuoso using "Retain reference library (No Merge)"

Category: Digital Implementation

By naderi
•
updated over 17 years ago by BobD

3 replies • 2569 views
Discussion

Power estimation after synthesis and Place-&-route

Category: Digital Implementation

By naderi
•
started over 17 years ago

0 replies • 834 views

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