Digital Implementation

Latest Posts

Discussion

encounter SEGV internal error (with optDesign -postRoute)

Category: Digital Implementation

By MadapusiSriniv
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updated over 7 years ago by Kari

2 replies • 1508 views
Discussion

POwer routing : Top level Block PG pin routing

Category: Digital Implementation

By remi pallas
•
updated over 7 years ago by remi pallas

2 replies • 15450 views
Discussion

Encounter via placement rules

Category: Digital Implementation

By masserg
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started over 7 years ago

0 replies • 5212 views
Discussion

ccopt ignore sink - common ui

Category: Digital Implementation

By Yemelya
•
updated over 7 years ago by HDar

2 replies • 3493 views
Discussion

output pin capacitance

Category: Digital Implementation

By HDar
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started over 7 years ago

0 replies • 13381 views
Discussion

INNOVUS: turned off during import design

Category: Digital Implementation

By Anklon
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updated over 7 years ago by Anklon

2 replies • 15098 views
Discussion

Static Rail Analysis Problem

Category: Digital Implementation

By Suhas Shivaprakash
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updated over 7 years ago by darnet341

1 replies • 15046 views
Discussion

Level-shifter cells are removed after placement

Category: Digital Implementation

By manpmanp
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updated over 7 years ago by manpmanp

2 replies • 14396 views
Discussion

CPF - two primary_power_nets for one power domain (different virtual power domains for different voltage sites of an IP block)

Category: Digital Implementation

By manpmanp
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started over 7 years ago

0 replies • 3155 views
Discussion

Generating ITF file from ICT file?

Category: Digital Implementation

By tessier5894
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started over 7 years ago

0 replies • 2368 views
Discussion

tie cell net connection missing

Category: Digital Implementation

By iamravikiran
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started over 7 years ago

0 replies • 12796 views
Discussion

I/O pad pins are placed randomly (each pad_pin is not placed on the corresponding pad)

Category: Digital Implementation

By Andorra
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started over 7 years ago

0 replies • 1140 views
Discussion

Core filler not getting inserted below vertical power stripe

Category: Digital Implementation

By Smriti Gupta
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started over 7 years ago

0 replies • 13127 views
Discussion

Metal-layer Cells

Category: Digital Implementation

By kevinSh
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started over 7 years ago

0 replies • 13025 views
Discussion

Clock tree synthesis (ccopt): where set_clock_latency has been defined?

Category: Digital Implementation

By Clidre
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updated over 7 years ago by TungVo

1 replies • 16793 views

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