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Digital Implementation

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  • Discussion

    Power Breakdown (sequential, combinational, I/O) report for hierarichal design

    Category: Digital Implementation

    By AliShami

    •

    started over 14 years ago

    0 replies • 907 views
  • Discussion

    Creating a netlist in Orcad 16.0

    Category: Digital Implementation

    By Elixz

    •

    updated over 14 years ago by Elixz

    1 replies • 14505 views
  • Discussion

    cadence encounter flow

    Category: Digital Implementation

    By shakun

    •

    updated over 14 years ago by shakun

    6 replies • 17481 views
  • Discussion

    dbgAutoCellFunction and RC scale factors

    Category: Digital Implementation

    By archive

    •

    updated over 14 years ago by Kari

    5 replies • 16478 views
  • Discussion

    How characterize latches or flip-flops (create tlf file) using SignalStorm.

    Category: Digital Implementation

    By TiNat

    •

    updated over 14 years ago by TiNat

    1 replies • 5914 views
  • Discussion

    delta slew/transition used for library setup time in SI

    Category: Digital Implementation

    By jkeefer

    •

    started over 14 years ago

    0 replies • 759 views
  • Discussion

    NRDB-51 warning

    Category: Digital Implementation

    By gpremala

    •

    started over 14 years ago

    0 replies • 14184 views
  • Discussion

    Documentation for MMMC flow with CPF

    Category: Digital Implementation

    By mamsadegh

    •

    updated over 14 years ago by tstark

    4 replies • 19408 views
  • Discussion

    What does it mean "Honor LEF defined pitches for advanced node" in First encounter

    Category: Digital Implementation

    By talpiot

    •

    started over 14 years ago

    0 replies • 1458 views
  • Discussion

    How to avoid a group of cell from getting optimised

    Category: Digital Implementation

    By crystee

    •

    updated over 14 years ago by fitz

    1 replies • 15056 views
  • Discussion

    preserve module ports

    Category: Digital Implementation

    By PradyK

    •

    updated over 14 years ago by fitz

    1 replies • 15403 views
  • Discussion

    understand the "COVER" placement status

    Category: Digital Implementation

    By dreamhunter

    •

    updated over 14 years ago by wally1

    1 replies • 3034 views
  • Discussion

    NRDB-1005 warning

    Category: Digital Implementation

    By mwhite

    •

    updated over 14 years ago by wally1

    3 replies • 15353 views
  • Discussion

    LEC - gated clock latches "Unreachable"

    Category: Digital Implementation

    By Yemelya

    •

    updated over 14 years ago by piyushoct

    6 replies • 6922 views
  • Discussion

    RAM Retention Test pattern generation with Encounter Test

    Category: Digital Implementation

    By dp2402

    •

    updated over 14 years ago by dp2402

    1 replies • 15222 views
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