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Digital Implementation

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  • Discussion

    SOC ENcounter : Too Many Violations in a Single AND Gate

    Category: Digital Implementation

    By Sohaib Qazi

    •

    started over 14 years ago

    0 replies • 14472 views
  • Discussion

    Library scaling

    Category: Digital Implementation

    By mamsadegh

    •

    updated over 14 years ago by mamsadegh

    1 replies • 15302 views
  • Discussion

    cell function vs when condition for case_analysis

    Category: Digital Implementation

    By abc12

    •

    started over 14 years ago

    0 replies • 14182 views
  • Discussion

    Different voltage for bulk pins of logic gates

    Category: Digital Implementation

    By sandeepmiryala

    •

    started over 14 years ago

    0 replies • 14590 views
  • Discussion

    min step & min area

    Category: Digital Implementation

    By crystee

    •

    updated over 14 years ago by crystee

    2 replies • 2039 views
  • Discussion

    **DIAG message while running a db command

    Category: Digital Implementation

    By tiEngr

    •

    updated over 14 years ago by wally1

    3 replies • 15294 views
  • Discussion

    SOC Encounter :: Layout Routing Issues

    Category: Digital Implementation

    By Sohaib Qazi

    •

    updated over 14 years ago by Anjana

    3 replies • 17334 views
  • Discussion

    Cell delay estimation for pre route and post route

    Category: Digital Implementation

    By gops

    •

    updated over 14 years ago by Kari

    10 replies • 19972 views
  • Discussion

    QRC from within encounter - n2n file

    Category: Digital Implementation

    By timoue

    •

    started over 14 years ago

    0 replies • 402 views
  • Discussion

    How to update a tech LEF in an opened design in EDI 11

    Category: Digital Implementation

    By chadhale

    •

    updated over 14 years ago by chadhale

    1 replies • 15945 views
  • Discussion

    pin positions

    Category: Digital Implementation

    By KVBABU

    •

    updated over 14 years ago by Kari

    1 replies • 14671 views
  • Discussion

    remove inverter pairs from design?

    Category: Digital Implementation

    By bluebear

    •

    updated over 14 years ago by bluebear

    6 replies • 18590 views
  • Discussion

    Error while reading Verilog File [Encounter 10.11]

    Category: Digital Implementation

    By nisshu

    •

    started over 14 years ago

    0 replies • 14469 views
  • Discussion

    Getting associated library cell name for a instance in ets

    Category: Digital Implementation

    By abhingp01

    •

    updated over 14 years ago by abhingp01

    4 replies • 22071 views
  • Discussion

    SOC - how do i flatten hierarchy design

    Category: Digital Implementation

    By bluebear

    •

    updated over 14 years ago by bluebear

    3 replies • 5536 views
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