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Digital Implementation

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  • Discussion

    Hspice memory error

    Category: Digital Implementation

    By superman321 superman321

    •

    started over 14 years ago

    0 replies • 12996 views
  • Discussion

    hoho, Bob, 1 question again for CTS

    Category: Digital Implementation

    By archive archive

    •

    updated over 14 years ago by BobD

    7 replies • 14038 views
  • Discussion

    spare logic is not tied up/down properly after ECO route

    Category: Digital Implementation

    By achilles achilles

    •

    updated over 14 years ago by J2mh

    1 replies • 853 views
  • Discussion

    Encounter Library Characterizer alf2vhdl problem

    Category: Digital Implementation

    By eklikeroomys eklikeroomys

    •

    updated over 14 years ago by J2mh

    1 replies • 12888 views
  • Discussion

    How to calculate the channel spacing between macros?

    Category: Digital Implementation

    By Ashok Nellore Ashok Nellore

    •

    updated over 14 years ago by J2mh

    1 replies • 17895 views
  • Discussion

    ncelab: segmentation of a signal

    Category: Digital Implementation

    By konx konx

    •

    updated over 14 years ago by diablo

    5 replies • 13579 views
  • Discussion

    report_transitive_fanin

    Category: Digital Implementation

    By jaso jaso

    •

    started over 14 years ago

    0 replies • 12694 views
  • Discussion

    From Verilog to layout - Flow problems

    Category: Digital Implementation

    By konx konx

    •

    started over 14 years ago

    0 replies • 842 views
  • Discussion

    Proving that a given netlist A results in better layout than netlist B

    Category: Digital Implementation

    By asinghct asinghct

    •

    updated over 14 years ago by Kari

    1 replies • 12920 views
  • Discussion

    Consider a std cell as a macro to do sroute

    Category: Digital Implementation

    By lohith21 lohith21

    •

    updated over 14 years ago by Kari

    5 replies • 13984 views
  • Discussion

    How can I cut a routing blockage in FE?

    Category: Digital Implementation

    By archive archive

    •

    updated over 14 years ago by patrice06

    7 replies • 17248 views
  • Discussion

    Encounter / TimeDesign / ClkGate

    Category: Digital Implementation

    By Yemelya Yemelya

    •

    updated over 14 years ago by Kari

    3 replies • 13559 views
  • Discussion

    Running time with VCD annotation

    Category: Digital Implementation

    By vaswan vaswan

    •

    updated over 14 years ago by Scrivner

    1 replies • 13090 views
  • Discussion

    Confusion related to fixing setup violation using ECO.....................:(

    Category: Digital Implementation

    By Hardeep Hardeep

    •

    started over 14 years ago

    0 replies • 12839 views
  • Discussion

    placeDesign uses trialRoute

    Category: Digital Implementation

    By Johann Glaser Johann Glaser

    •

    started over 14 years ago

    0 replies • 12964 views
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