Digital Implementation

hoho, Bob, 1 question again for CTS

Category: Digital Implementation

spare logic is not tied up/down properly after ECO route

Category: Digital Implementation

Encounter Library Characterizer alf2vhdl problem

Category: Digital Implementation

How to calculate the channel spacing between macros?

Category: Digital Implementation

ncelab: segmentation of a signal

Category: Digital Implementation

report_transitive_fanin

Category: Digital Implementation

From Verilog to layout - Flow problems

Category: Digital Implementation

Proving that a given netlist A results in better layout than netlist B

Category: Digital Implementation

Consider a std cell as a macro to do sroute

Category: Digital Implementation

How can I cut a routing blockage in FE?

Category: Digital Implementation

Encounter / TimeDesign / ClkGate

Category: Digital Implementation

Running time with VCD annotation

Category: Digital Implementation

Confusion related to fixing setup violation using ECO.....................:(

Category: Digital Implementation

placeDesign uses trialRoute

Category: Digital Implementation

"optDesign -preCTS" doesn't seem to be optimizing

Category: Digital Implementation