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Digital Implementation

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  • Discussion

    create_generated_clock works?

    Category: Digital Implementation

    By mwhite mwhite

    •

    updated over 14 years ago by wally1

    1 replies • 14552 views
  • Discussion

    ELC Simulation { ... dc ??? } Documentation

    Category: Digital Implementation

    By Natan00 Natan00

    •

    started over 14 years ago

    0 replies • 12609 views
  • Discussion

    Compatibility problem between ELC and Verilog-A

    Category: Digital Implementation

    By Bastien Bastien

    •

    updated over 14 years ago by rangha

    1 replies • 12954 views
  • Discussion

    Number of clock gated components

    Category: Digital Implementation

    By Shivareddy Shivareddy

    •

    updated over 14 years ago by wally1

    3 replies • 13303 views
  • Discussion

    a doubt while designing a cmos inverter in cadence 614

    Category: Digital Implementation

    By suman samui suman samui

    •

    started over 14 years ago

    0 replies • 12541 views
  • Discussion

    Timing Engine isues **ERROR: (TA-152) complaining about generated clock edges (was: an Error during placement?)

    Category: Digital Implementation

    By icmaple icmaple

    •

    updated over 14 years ago by Shivareddy

    5 replies • 18875 views
  • Discussion

    How to get screen copies under specific view condition

    Category: Digital Implementation

    By Teru Teru

    •

    updated over 14 years ago by Teru

    1 replies • 12921 views
  • Discussion

    ELC library charachterization: db_prepare, gate file

    Category: Digital Implementation

    By scudex scudex

    •

    started over 14 years ago

    0 replies • 12563 views
  • Discussion

    optDesign removes fillers

    Category: Digital Implementation

    By Johann Glaser Johann Glaser

    •

    updated over 14 years ago by Johann Glaser

    4 replies • 15509 views
  • Discussion

    SDF Errors

    Category: Digital Implementation

    By tswong tswong

    •

    updated over 14 years ago by MzQuarter

    5 replies • 17531 views
  • Discussion

    DEF import to Virtuoso

    Category: Digital Implementation

    By superman321 superman321

    •

    updated over 14 years ago by scudex

    4 replies • 14870 views
  • Discussion

    SDF Errors: ncelab: *W,SDFGENNF

    Category: Digital Implementation

    By legolas legolas

    •

    started over 14 years ago

    0 replies • 557 views
  • Discussion

    ETV Vs Spice cell delay Values

    Category: Digital Implementation

    By deeps deeps

    •

    started over 14 years ago

    0 replies • 12558 views
  • Discussion

    About dbCommands

    Category: Digital Implementation

    By Vio719 Vio719

    •

    updated over 14 years ago by Vio719

    2 replies • 13105 views
  • Discussion

    clk nets change to dontTouchNets during CTS in Low-power Design.

    Category: Digital Implementation

    By kkhhh kkhhh

    •

    started over 14 years ago

    0 replies • 12574 views
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