Functional Verification

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Discussion

Communication between e and SV

Category: Functional Verification

By YM KIM
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updated over 15 years ago by StephenH

3 replies • 13463 views
Discussion

a problem about simulation

Category: Functional Verification

By Nathen
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updated over 15 years ago by themperek

1 replies • 13012 views
Discussion

ICCR union usage

Category: Functional Verification

By jzingman
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updated over 16 years ago by nlin

1 replies • 13111 views
Discussion

Continue_error

Category: Functional Verification

By SpecMAN INFANT
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updated over 16 years ago by MVSI

3 replies • 13338 views
Discussion

Unresolved adater ERR_DID_NOT_FIND_ADAPTER

Category: Functional Verification

By random
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updated over 16 years ago by random

2 replies • 13444 views
Discussion

Simulation Problem : resolving X of a un-initialized f/f whose output feedback to itself thru some logic

Category: Functional Verification

By iclcle
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updated over 16 years ago by StephenH

1 replies • 2542 views
Discussion

test to write and read registers with field order like packing.low

Category: Functional Verification

By mkyang
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updated over 16 years ago by StephenH

1 replies • 12843 views
Discussion

Verilog, System Verilog and SystemC

Category: Functional Verification

By jasonkee111
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updated over 16 years ago by mstellfox

3 replies • 17054 views
Discussion

generate of specman (vs) randomize of systemverilog

Category: Functional Verification

By onkarkk
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updated over 16 years ago by onkarkk

4 replies • 15337 views
Discussion

Simulation problem: unwanted zero-width glitch

Category: Functional Verification

By ridgemao
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updated over 16 years ago by Shalom B

3 replies • 19897 views
Discussion

FSM coverage and generate block

Category: Functional Verification

By karlsmartin
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updated over 16 years ago by StephenH

1 replies • 14063 views
Discussion

enum type dynamic array is giving an error with ius8.2-s006

Category: Functional Verification

By 123454321
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updated over 16 years ago by archive

1 replies • 12984 views
Discussion

empty/illegal list of parameters

Category: Functional Verification

By rashmikant
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updated over 16 years ago by archive

1 replies • 1129 views
Discussion

IUS82s012: is this legal "for ( genvar g = 0; g < 4; ++g ) ..."?

Category: Functional Verification

By cubicle82
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updated over 16 years ago by cubicle82

2 replies • 1742 views
Discussion

Verilog Monitor to Check 'X' state of a Clock from the DUT.

Category: Functional Verification

By RaghavNS
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updated over 16 years ago by Mickey

2 replies • 7803 views

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