Functional Verification

Latest Posts

Discussion

Interface port coercion

Category: Functional Verification

By int19

$usertype
•
updated over 6 years ago by OmidTaheri

3 replies • 21060 views
Discussion

Design library not defined while reading module with ncsim

Category: Functional Verification

By cuonghl

$usertype
•
updated over 6 years ago by cuonghl

4 replies • 21466 views
Discussion

[IMC] Toggle coverage report

Category: Functional Verification

By NabilE

$usertype
•
updated over 6 years ago by NabilE

2 replies • 16996 views
Discussion

How to make defparam disappear in netlist generated by NC-verilog in Cadence

Category: Functional Verification

By Darkhorse

$usertype
•
updated over 6 years ago by StephenH

1 replies • 14340 views
Discussion

VPlan Report- links for each test

Category: Functional Verification

By mxm1489

$usertype
•
updated over 6 years ago by StephenH

1 replies • 1563 views
Discussion

VManager wrongly imports failed test as passed

Category: Functional Verification

By GxxCxx

$usertype
•
updated over 6 years ago by StephenH

1 replies • 15536 views
Discussion

Export a Breakpoint

Category: Functional Verification

By Elnic8745

$usertype
•
updated over 6 years ago by Doug Koslow

3 replies • 15554 views
Discussion

NCLaunch VHDL compiler *F,DLUNNE error

Category: Functional Verification

By yavuzselim

$usertype
•
started over 6 years ago

0 replies • 1165 views
Discussion

vManager tool gives this error-"Error:Project Environment Selection is required by server,and must be set on this mode"

Category: Functional Verification

By rahul97

$usertype
•
updated over 6 years ago by DerekG0

3 replies • 3239 views
Discussion

$xm_deposit in gate level simulation

Category: Functional Verification

By mxm1489

$usertype
•
updated over 6 years ago by mxm1489

2 replies • 19275 views
Discussion

Dumping only last 1ms log file information in irun/xrun

Category: Functional Verification

By deeps4

$usertype
•
updated over 6 years ago by deeps4

6 replies • 7005 views
Discussion

How to effectively browse verilog source in Cadence

Category: Functional Verification

By DonVerilog

$usertype
•
updated over 6 years ago by Andrew Beckett

3 replies • 15259 views
Discussion

How to effectively browse verilog source in Cadence

Category: Functional Verification

By DonVerilog

$usertype
•
started over 6 years ago

0 replies • 13680 views
Discussion

How do I control probe start/stop in ncsim from embedded CPU?

Category: Functional Verification

By Ncsim User 1

$usertype
•
updated over 6 years ago by MayurAna

4 replies • 8127 views
Discussion

Initiating tcl script in Xcelium

Category: Functional Verification

By Khan190

$usertype
•
updated over 6 years ago by StephenH

1 replies • 23177 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.