Functional Verification

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Discussion

Dumping only last 1ms log file information in irun/xrun

Category: Functional Verification

By deeps4

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updated over 6 years ago by deeps4

6 replies • 7344 views
Discussion

How to effectively browse verilog source in Cadence

Category: Functional Verification

By DonVerilog

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updated over 6 years ago by Andrew Beckett

3 replies • 15732 views
Discussion

How to effectively browse verilog source in Cadence

Category: Functional Verification

By DonVerilog

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started over 6 years ago

0 replies • 14052 views
Discussion

How do I control probe start/stop in ncsim from embedded CPU?

Category: Functional Verification

By Ncsim User 1

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updated over 6 years ago by MayurAna

4 replies • 8363 views
Discussion

Initiating tcl script in Xcelium

Category: Functional Verification

By Khan190

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updated over 6 years ago by StephenH

1 replies • 23839 views
Discussion

Macro in `include compiler directive.

Category: Functional Verification

By VerificationMike

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updated over 6 years ago by VerificationMike

6 replies • 24000 views
Discussion

How to Setup Xcellium to run on Ubuntu

Category: Functional Verification

By CommLogicDesign

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updated over 6 years ago by StephenH

4 replies • 24616 views
Discussion

a test runs differently if I use the -svseed command line switch or I set the seed via tcl and then give run

Category: Functional Verification

By AlexOgheri

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updated over 6 years ago by StephenH

1 replies • 3932 views
Discussion

Issue with merging code coverage with different parameter values written inside generate block

Category: Functional Verification

By Btarpara

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updated over 6 years ago by StephenH

1 replies • 16495 views
Discussion

UVM Register viewer

Category: Functional Verification

By Meghana BN

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updated over 6 years ago by Meghana BN

2 replies • 16829 views
Discussion

Is it possible to do formal verification of firmware related functions in JasperGold?

Category: Functional Verification

By zainkabir

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updated over 6 years ago by StephenH

1 replies • 14578 views
Discussion

Reading SVSEED set by IUS,vamanger

Category: Functional Verification

By adwait

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updated over 6 years ago by Damn

3 replies • 3962 views
Discussion

Usage of verilog compiler directive in TCL

Category: Functional Verification

By usiciliani

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updated over 6 years ago by NineLights

5 replies • 19226 views
Discussion

System Verilog Assertions

Category: Functional Verification

By Manasy M

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updated over 6 years ago by Manasy M

4 replies • 19365 views
Discussion

Reading an input file using std.textio

Category: Functional Verification

By rafaelkl

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updated over 6 years ago by rafaelkl

5 replies • 17076 views

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