Functional Verification

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Discussion

Uninitialized Clock Gate Cells

Category: Functional Verification

By Bart Yount

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started over 11 years ago

0 replies • 14547 views
Discussion

case () inside gives errors with ncvlog

Category: Functional Verification

By mkamal

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updated over 11 years ago by Shalom B

2 replies • 20990 views
Discussion

coverage option weight

Category: Functional Verification

By Umar Farooq

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updated over 11 years ago by Aurelian Amiq

1 replies • 23091 views
Discussion

Mapping Libraries

Category: Functional Verification

By Swimteam

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started over 11 years ago

0 replies • 14588 views
Discussion

Error : Overflow, divider cannot be zero

Category: Functional Verification

By bharathwajan

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updated over 11 years ago by Nagamohan

1 replies • 14719 views
Discussion

Hierarchical Coverage

Category: Functional Verification

By Umar Farooq

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started over 11 years ago

0 replies • 13791 views
Discussion

Where can I get the equivalent circuit of device model?

Category: Functional Verification

By youngdd

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started over 11 years ago

0 replies • 13809 views
Discussion

Square Wave as input signal

Category: Functional Verification

By Pavan Garate

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updated over 11 years ago by oldmouldy

1 replies • 23018 views
Discussion

vManager Failed: Unexpected error ( Out of memory )

Category: Functional Verification

By JennyYang

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updated over 11 years ago by JennyYang

4 replies • 18618 views
Discussion

INCISIV132/122 does not support some systemverilog 2012 coverage coding

Category: Functional Verification

By JennyYang

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updated over 11 years ago by StephenH

2 replies • 1135 views
Discussion

Does irun 12.20 support multi-core simulation and how to do so

Category: Functional Verification

By JennyYang

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updated over 11 years ago by JennyYang

4 replies • 17956 views
Discussion

How to suppress these three mem_error/warning/abnormal transition messages

Category: Functional Verification

By usha sudhagar

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started over 11 years ago

0 replies • 1150 views
Discussion

query on scope of events in e language

Category: Functional Verification

By jaichandra

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updated over 11 years ago by jaichandra

2 replies • 14605 views
Discussion

How to suppress the warning -- ASSERT/WARNING (time 277932200 PS) from package ieee.NUMERIC_STD

Category: Functional Verification

By usha sudhagar

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updated over 11 years ago by muffi

1 replies • 7173 views
Discussion

Promlem with markers

Category: Functional Verification

By Mozak

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started over 11 years ago

0 replies • 14668 views

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