Functional Verification

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Discussion

How I can get test status from specman e at sv testbench

Category: Functional Verification

By KBragin

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updated over 11 years ago by hannes

1 replies • 5660 views
Discussion

increase virtual memory to sn_compile.sh

Category: Functional Verification

By amirb

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updated over 11 years ago by hannes

7 replies • 16927 views
Discussion

Setting vhdl tb generic using irun command

Category: Functional Verification

By itsonlyme

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updated over 11 years ago by itsonlyme

8 replies • 20075 views
Discussion

How can I dump waveform using irun uder UVM environment

Category: Functional Verification

By bbpfancy

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updated over 11 years ago by StephenH

1 replies • 18170 views
Discussion

Breakpoints in simvision(Incisiv Simulator)

Category: Functional Verification

By subrahmanya

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updated over 11 years ago by subrahmanya

2 replies • 3196 views
Discussion

ncprotect when using user-defined keys

Category: Functional Verification

By James Bailey

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started over 11 years ago

0 replies • 15758 views
Discussion

Functional Coverage Question

Category: Functional Verification

By ashfaqh

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updated over 11 years ago by StephenH

2 replies • 16164 views
Discussion

In UVM is there any Inheritance like "Specman e when Inheritance"..

Category: Functional Verification

By Selvavinayak

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updated over 11 years ago by Tudor Timi

1 replies • 1318 views
Discussion

Bind SVA to VHDL Enumerated Type

Category: Functional Verification

By rlanier

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updated over 11 years ago by Tudor Timi

1 replies • 15063 views
Discussion

Problem when running simulation with Verilog-AMS and SystemVerilog together with irun

Category: Functional Verification

By solomonchoi

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updated over 11 years ago by StephenH

3 replies • 20935 views
Discussion

Black boxing issue in IFV

Category: Functional Verification

By niraj10

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updated over 11 years ago by StephenH

1 replies • 14147 views
Discussion

I can't find "Part Manager" option in OrCad 16.3

Category: Functional Verification

By cimo

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updated over 11 years ago by AniketM

5 replies • 8028 views
Discussion

Envelop Following Analyses for Switching Amplifiers

Category: Functional Verification

By Mazia

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started over 11 years ago

0 replies • 13283 views
Discussion

Passing parameters form verilog to systemC

Category: Functional Verification

By jbriquet

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updated over 11 years ago by jbriquet

1 replies • 14108 views
Discussion

UVM Sequence

Category: Functional Verification

By DesignVerif

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updated over 11 years ago by DesignVerif

4 replies • 15165 views

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