Functional Verification

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Discussion

ADE L Outputs Window does not work

Category: Functional Verification

By hoorayitsjohn

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updated over 11 years ago by StephenH

1 replies • 14960 views
Discussion

UVC Source Synchronous Interface

Category: Functional Verification

By rlanier

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updated over 11 years ago by StephenH

1 replies • 14521 views
Discussion

ICCR: toggle exclude for bits of a bus

Category: Functional Verification

By Cadence Forum

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updated over 11 years ago by StephenH

9 replies • 19489 views
Discussion

net connectivity at the top level using TCL

Category: Functional Verification

By freitas

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updated over 11 years ago by freitas

2 replies • 14824 views
Discussion

Capture project conversion

Category: Functional Verification

By Mael LM

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updated over 11 years ago by oldmouldy

1 replies • 14701 views
Discussion

How I can get test status from specman e at sv testbench

Category: Functional Verification

By KBragin

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updated over 11 years ago by hannes

1 replies • 5719 views
Discussion

increase virtual memory to sn_compile.sh

Category: Functional Verification

By amirb

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updated over 11 years ago by hannes

7 replies • 17451 views
Discussion

Setting vhdl tb generic using irun command

Category: Functional Verification

By itsonlyme

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updated over 11 years ago by itsonlyme

8 replies • 20695 views
Discussion

How can I dump waveform using irun uder UVM environment

Category: Functional Verification

By bbpfancy

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updated over 11 years ago by StephenH

1 replies • 18608 views
Discussion

Breakpoints in simvision(Incisiv Simulator)

Category: Functional Verification

By subrahmanya

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updated over 11 years ago by subrahmanya

2 replies • 3316 views
Discussion

ncprotect when using user-defined keys

Category: Functional Verification

By James Bailey

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started over 11 years ago

0 replies • 16199 views
Discussion

Functional Coverage Question

Category: Functional Verification

By ashfaqh

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updated over 11 years ago by StephenH

2 replies • 16584 views
Discussion

In UVM is there any Inheritance like "Specman e when Inheritance"..

Category: Functional Verification

By Selvavinayak

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updated over 11 years ago by Tudor Timi

1 replies • 1396 views
Discussion

Bind SVA to VHDL Enumerated Type

Category: Functional Verification

By rlanier

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updated over 11 years ago by Tudor Timi

1 replies • 15446 views
Discussion

Problem when running simulation with Verilog-AMS and SystemVerilog together with irun

Category: Functional Verification

By solomonchoi

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updated over 11 years ago by StephenH

3 replies • 21495 views

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