Functional Verification

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How to change the default behavior of IES9.2 for default coverage type (i.e. from per_instance to per_type coverage)

Category: Functional Verification

By Ayush

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updated over 15 years ago by Ayush

2 replies • 14035 views
Discussion

Elaborate Verilog and VHDL mixed language design

Category: Functional Verification

By archive

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started over 15 years ago

0 replies • 14744 views
Discussion

*E,OBJACC: Object must have write access: <object name>

Category: Functional Verification

By prkroon

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updated over 15 years ago by prkroon

4 replies • 6122 views
Discussion

What is the difference between E and Vera

Category: Functional Verification

By Raviram80

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updated over 15 years ago by teamspecman

2 replies • 15958 views
Discussion

Tracking signal values in simvision

Category: Functional Verification

By bgpradeep

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updated over 15 years ago by Tikesh

1 replies • 17069 views
Discussion

missing cdn_e_utility in vr_ahb (09.20.003-s )

Category: Functional Verification

By sunindew

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updated over 15 years ago by Mirit Fromovic

1 replies • 13931 views
Discussion

Event capture After Rerun in Specman

Category: Functional Verification

By JatinSavani

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started over 15 years ago

0 replies • 13639 views
Discussion

Specman Documentation Query

Category: Functional Verification

By Sarvesh

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updated over 15 years ago by swamiv

3 replies • 14812 views
Discussion

Vexp source causes Allegro to crash

Category: Functional Verification

By fmacc

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started over 15 years ago

0 replies • 13950 views
Discussion

Assertions

Category: Functional Verification

By Raviram80

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updated over 15 years ago by Raviram80

2 replies • 14688 views
Discussion

Stubs in E language

Category: Functional Verification

By Raviram80

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updated over 15 years ago by StephenH

2 replies • 14504 views
Discussion

Specman : check() and sys.finalize()

Category: Functional Verification

By Raviram80

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updated over 15 years ago by StephenH

1 replies • 14362 views
Discussion

BFM and Driver

Category: Functional Verification

By Raviram80

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updated over 15 years ago by StephenH

3 replies • 17040 views
Discussion

explenation on the verilog_wire() method

Category: Functional Verification

By archive

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updated over 15 years ago by sgor

2 replies • 14446 views
Discussion

System Verilog with Spice *F,INTERR - cu_check_port_var_aca

Category: Functional Verification

By GraemeNunn

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updated over 15 years ago by StephenH

1 replies • 1323 views

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