Functional Verification

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Discussion

Specman : check() and sys.finalize()

Category: Functional Verification

By Raviram80
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updated over 16 years ago by StephenH

1 replies • 15067 views
Discussion

BFM and Driver

Category: Functional Verification

By Raviram80
•
updated over 16 years ago by StephenH

3 replies • 18206 views
Discussion

explenation on the verilog_wire() method

Category: Functional Verification

By archive
•
updated over 16 years ago by sgor

2 replies • 15235 views
Discussion

System Verilog with Spice *F,INTERR - cu_check_port_var_aca

Category: Functional Verification

By GraemeNunn
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updated over 16 years ago by StephenH

1 replies • 1629 views
Discussion

Testbench with non-unique module names in sub-blocks

Category: Functional Verification

By mattyc
•
updated over 16 years ago by StephenH

2 replies • 19719 views
Discussion

starting an executable from specman, how to ?

Category: Functional Verification

By archive
•
updated over 16 years ago by archive

2 replies • 15117 views
Discussion

functional coverage result issue at the end of simulation

Category: Functional Verification

By Bhabani
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updated over 16 years ago by StephenH

1 replies • 14830 views
Discussion

AMS Designer Incisive Use Model - AIUM

Category: Functional Verification

By KartikAMS
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started over 16 years ago

0 replies • 1030 views
Discussion

Illegal Character [Error ALG0065]

Category: Functional Verification

By ddra90n
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updated over 16 years ago by oldmouldy

1 replies • 15187 views
Discussion

Simvision plugins

Category: Functional Verification

By Vincent DEBOUT
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updated over 16 years ago by Vincent DEBOUT

3 replies • 16407 views
Discussion

Viewing Tasks / Functions in waveforms

Category: Functional Verification

By Sarvesh
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updated over 16 years ago by tpylant

1 replies • 15206 views
Discussion

*F,LCFAIL: (LM -4) ....

Category: Functional Verification

By mmk23
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updated over 16 years ago by StephenH

1 replies • 2460 views
Discussion

Problem compiling FVSVOVM Xbar package

Category: Functional Verification

By archive
•
updated over 16 years ago by StephenH

6 replies • 18691 views
Discussion

VHDL & SystemVerilog Connection

Category: Functional Verification

By ssan
•
started over 16 years ago

0 replies • 1345 views
Discussion

how to run ovm cookbook example by IUS?

Category: Functional Verification

By RomanDW
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updated over 16 years ago by pcarzola

4 replies • 15950 views

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