Logic Design

Latest Posts

Discussion

UNCONNECTED NETS in GENUS NETLIST!

Category: Logic Design

By AireenAmir
•
updated over 4 years ago by Rameen

1 replies • 15557 views
Discussion

Genus VHDL 2008 Unconstrained array - Illegal element type for composite type. [VHDLPT-567] [read_hdl]

Category: Logic Design

By FlorianP
•
updated over 4 years ago by FlorianP

2 replies • 10177 views
Discussion

RTL synthesis fault

Category: Logic Design

By nokta
•
updated over 4 years ago by Rameen

6 replies • 20671 views
Discussion

What's the advantage for declaration different clock domain in Genus

Category: Logic Design

By NickK
•
updated over 4 years ago by Dimo M

1 replies • 6420 views
Discussion

What is the command for opening the Xcelium Simulator ?

Category: Logic Design

By Sandeep29
•
updated over 4 years ago by Dimo M

1 replies • 32783 views
Discussion

Compiling Xilinx libraries using Xcleium

Category: Logic Design

By rohanj
•
updated over 4 years ago by rohanj

4 replies • 18306 views
Discussion

Reporting non-RC gated flops

Category: Logic Design

By Max Bjurling
•
updated over 4 years ago by Max Bjurling

2 replies • 15759 views
Discussion

Genus - Hierarchy

Category: Logic Design

By Stratis
•
updated over 4 years ago by Dimo M

1 replies • 7640 views
Discussion

VHDL IEEE Library not recognized by RTL Compiler or Genus

Category: Logic Design

By YuntaoLiu
•
updated over 4 years ago by Dimo M

1 replies • 15083 views
Discussion

Conformal-ECO priority of picking freed cells and sparecells

Category: Logic Design

By Mihu
•
started over 4 years ago

0 replies • 13401 views
Discussion

VHDL-613 error inside declarative region

Category: Logic Design

By carlosgewehr
•
started over 4 years ago

0 replies • 12806 views
Discussion

Force cell equivalence between same-footprint and same-functionality hard-macros in Conformal LEC

Category: Logic Design

By Luca Pacher
•
updated over 4 years ago by AndreasWiener

1 replies • 15146 views
Discussion

Genus advices on how to handle power and analog signals

Category: Logic Design

By abettati
•
started over 4 years ago

0 replies • 13651 views
Discussion

Error in Cadence RTL Compiler when estimating Power using VCD

Category: Logic Design

By RileyDylan
•
started over 4 years ago

0 replies • 13187 views
Discussion

how to debug the misbehaving scheduling of sequential logic

Category: Logic Design

By ChrisKAustin
•
started over 4 years ago

0 replies • 13147 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.