Logic Design

Latest Posts

Discussion

how to identify unique nets connected to preset/clear pins of all FFs in a scope

Category: Logic Design

By Sporadic Crash
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updated over 11 years ago by grasshopper

1 replies • 1343 views
Discussion

delay between 2 signals

Category: Logic Design

By vvgulyaev
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updated over 11 years ago by grasshopper

1 replies • 6021 views
Discussion

conformal

Category: Logic Design

By Indira S
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started over 11 years ago

0 replies • 12743 views
Discussion

conformal lec

Category: Logic Design

By Indira S
•
started over 11 years ago

0 replies • 13177 views
Discussion

Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist

Category: Logic Design

By Rafeeq2129
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updated over 11 years ago by tstark

12 replies • 17392 views
Discussion

conformal_lec 12.0

Category: Logic Design

By Indira S
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updated over 11 years ago by tstark

1 replies • 13158 views
Discussion

Design Entry HDL - Disabling Constraint Manager

Category: Logic Design

By Crispy
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started over 11 years ago

0 replies • 783 views
Discussion

conformal

Category: Logic Design

By Indira S
•
started over 11 years ago

0 replies • 13469 views
Discussion

conformal -Lec

Category: Logic Design

By Indira S
•
updated over 11 years ago by tstark

1 replies • 4145 views
Discussion

Conformal- LEC

Category: Logic Design

By Indira S
•
updated over 11 years ago by tstark

1 replies • 2434 views
Discussion

Algorithm used for implementation of Division

Category: Logic Design

By S0MA
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updated over 11 years ago by S0MA

2 replies • 14300 views
Discussion

Instance name mismatch between .v and .sdf writen from RTL compiler

Category: Logic Design

By zczc999
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started over 11 years ago

0 replies • 13470 views
Discussion

Preserving structure in RTL Compiler

Category: Logic Design

By Aram Shahinyan
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updated over 11 years ago by grasshopper

7 replies • 18719 views
Discussion

CIS Schematic Page numbering

Category: Logic Design

By budnoel
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started over 11 years ago

0 replies • 12870 views
Discussion

How to set_current_module in RTL Compiler??

Category: Logic Design

By archive
•
updated over 11 years ago by jojo57006

10 replies • 17856 views

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