Logic Design

Latest Posts

Discussion

Genus : Tool coming out with "Killed"

Category: Logic Design

By sharadbrcm
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updated over 3 years ago by sharadbrcm

1 replies • 4649 views
Discussion

Best library structure (worklibs)

Category: Logic Design

By Ryic
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started over 3 years ago

0 replies • 9878 views
Discussion

xmvlog: *E,MULPAK

Category: Logic Design

By Yishay
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started over 3 years ago

0 replies • 5167 views
Discussion

Can Joules Report on wasted power on the inputs of a gated flop?

Category: Logic Design

By Falanke
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started over 3 years ago

0 replies • 10188 views
Discussion

Genus synthesis report

Category: Logic Design

By Kelly Yu
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updated over 3 years ago by Kelly Yu

2 replies • 14015 views
Discussion

Genus: Problem with long module name due to parameter types

Category: Logic Design

By pkarl
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updated over 3 years ago by pkarl

1 replies • 14106 views
Discussion

How to interpret area reported by Genus in mm2

Category: Logic Design

By abarajithan11
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started over 3 years ago

0 replies • 12750 views
Discussion

What kind of flops does state retention synthesis take?

Category: Logic Design

By iamKarthikBK
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started over 3 years ago

0 replies • 11714 views
Discussion

How to add logic when compile

Category: Logic Design

By BaoP
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started over 4 years ago

0 replies • 11920 views
Discussion

Check Constraints Problem

Category: Logic Design

By Dimitris Ant
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updated over 4 years ago by Dimo M

2 replies • 20892 views
Discussion

Tool for generating 'documentation friendly' schematics from RTL

Category: Logic Design

By gretzteam
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updated over 4 years ago by lstand

1 replies • 6567 views
Discussion

Default settings for cell mapping - Genus Synthesis (Legacy)

Category: Logic Design

By iamKarthikBK
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started over 4 years ago

0 replies • 6137 views
Discussion

Xcelium notation worklib:cell:view

Category: Logic Design

By Yakir
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started over 4 years ago

0 replies • 3834 views
Discussion

Get defines value from Xcelium simulation

Category: Logic Design

By Yakir
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started over 4 years ago

0 replies • 13952 views
Discussion

How to force RTL compiler to use a particular net name

Category: Logic Design

By deeps4
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updated over 4 years ago by Rameen

4 replies • 18591 views

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