Logic Design

Latest Posts

Discussion

how to identify unique nets connected to preset/clear pins of all FFs in a scope

Category: Logic Design

By Sporadic Crash

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updated over 11 years ago by grasshopper

1 replies • 1497 views
Discussion

delay between 2 signals

Category: Logic Design

By vvgulyaev

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updated over 11 years ago by grasshopper

1 replies • 6189 views
Discussion

conformal

Category: Logic Design

By Indira S

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started over 11 years ago

0 replies • 13428 views
Discussion

conformal lec

Category: Logic Design

By Indira S

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started over 11 years ago

0 replies • 13917 views
Discussion

Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist

Category: Logic Design

By Rafeeq2129

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updated over 11 years ago by tstark

12 replies • 19181 views
Discussion

conformal_lec 12.0

Category: Logic Design

By Indira S

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updated over 11 years ago by tstark

1 replies • 13937 views
Discussion

Design Entry HDL - Disabling Constraint Manager

Category: Logic Design

By Crispy

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started over 11 years ago

0 replies • 857 views
Discussion

conformal

Category: Logic Design

By Indira S

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started over 11 years ago

0 replies • 14236 views
Discussion

conformal -Lec

Category: Logic Design

By Indira S

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updated over 11 years ago by tstark

1 replies • 4577 views
Discussion

Conformal- LEC

Category: Logic Design

By Indira S

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updated over 11 years ago by tstark

1 replies • 2629 views
Discussion

Algorithm used for implementation of Division

Category: Logic Design

By S0MA

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updated over 11 years ago by S0MA

2 replies • 15241 views
Discussion

Instance name mismatch between .v and .sdf writen from RTL compiler

Category: Logic Design

By zczc999

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started over 11 years ago

0 replies • 14270 views
Discussion

Preserving structure in RTL Compiler

Category: Logic Design

By Aram Shahinyan

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updated over 11 years ago by grasshopper

7 replies • 20068 views
Discussion

CIS Schematic Page numbering

Category: Logic Design

By budnoel

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started over 12 years ago

0 replies • 13565 views
Discussion

How to set_current_module in RTL Compiler??

Category: Logic Design

By archive

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updated over 12 years ago by jojo57006

10 replies • 19171 views

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