Logic Design

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Discussion

RC - read_hdl

Category: Logic Design

By Yemelya

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updated over 12 years ago by Yemelya

2 replies • 5118 views
Discussion

Does clock power included in Power Report ?

Category: Logic Design

By dkhan

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updated over 12 years ago by dkhan

2 replies • 16064 views
Discussion

power differences after post-syn using VCD

Category: Logic Design

By leez2006

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updated over 12 years ago by leez2006

2 replies • 15442 views
Discussion

how to add synthesizable delay in design

Category: Logic Design

By yasir khan

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updated over 12 years ago by Paul Bibin

1 replies • 15367 views
Discussion

How to avoid unwanted removal of logic during synthesis

Category: Logic Design

By dkhan

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updated over 12 years ago by dkhan

2 replies • 19130 views
Discussion

RTL compiler command for retaining design hierarchy

Category: Logic Design

By dkhan

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updated over 12 years ago by dkhan

2 replies • 17308 views
Discussion

how to compare designware like DW02_multp with LEC

Category: Logic Design

By codefire

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updated over 12 years ago by conformalfan

3 replies • 15753 views
Discussion

Conformal LEC Dofile Arguments.

Category: Logic Design

By scrip

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updated over 12 years ago by tstark

3 replies • 18268 views
Discussion

RTL compiler to minimize area

Category: Logic Design

By Hamzah

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updated over 12 years ago by Hamzah

4 replies • 18648 views
Discussion

Creating a reset scan test using Encounter Test

Category: Logic Design

By glennramalho

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started over 12 years ago

0 replies • 13780 views
Discussion

set_false_path -through and set_load on the output ports

Category: Logic Design

By beginer

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updated over 12 years ago by grasshopper

1 replies • 2314 views
Discussion

How do I delete clock groups (created via set_clock_groups)

Category: Logic Design

By moogydmaxim

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updated over 12 years ago by grasshopper

1 replies • 15010 views
Discussion

How to use the Encounter RTL Compiler Super-Thread with Tivoli Workload LoadLeveler

Category: Logic Design

By lvcargnini

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updated over 12 years ago by grasshopper

1 replies • 15949 views
Discussion

cell_leakage_power

Category: Logic Design

By msanyal

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updated over 12 years ago by bmiller

1 replies • 13988 views
Discussion

Scan mode and scan chain control from internal registers

Category: Logic Design

By Sinjeetp

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updated over 12 years ago by Sinjeetp

4 replies • 17627 views

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