Logic Design

Latest Posts

Discussion

Unit names for vhdl and verilog

Category: Logic Design

By ras thomas
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updated over 16 years ago by ras thomas

1 replies • 13426 views
Discussion

why IUS so sloooooow ?

Category: Logic Design

By duckfly
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updated over 16 years ago by Adam Sherer

4 replies • 1312 views
Discussion

Power nets vs offpage connector

Category: Logic Design

By Jamez
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updated over 16 years ago by oldmouldy

1 replies • 13880 views
Discussion

ETS software crash

Category: Logic Design

By MarceloLucena
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updated over 16 years ago by MarceloLucena

1 replies • 12937 views
Discussion

Problems Saving in .SCH format

Category: Logic Design

By xmoix
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updated over 16 years ago by oldmouldy

1 replies • 13096 views
Discussion

license error on my system

Category: Logic Design

By havisingh
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updated over 16 years ago by havisingh

2 replies • 15313 views
Discussion

No binary/Encrypted TCL(tcl compiler) support in all cadence tools, but Yes in Synopsys!

Category: Logic Design

By iceda
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updated over 16 years ago by grasshopper

5 replies • 3852 views
Discussion

LEC Issue with falling edge clock gater cells

Category: Logic Design

By FredS
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updated over 16 years ago by croy

1 replies • 13439 views
Discussion

Overwriting messages warning in RC

Category: Logic Design

By shift
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updated over 16 years ago by shift

2 replies • 13340 views
Discussion

choosing a decision between buffer and inverter in CTS

Category: Logic Design

By mmkrcool
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started over 16 years ago

0 replies • 13104 views
Discussion

Layout

Category: Logic Design

By Hoda
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updated over 16 years ago by johannes

1 replies • 12837 views
Discussion

How to increase timing table dimensions in a lib file created from do_extract_model

Category: Logic Design

By vavendan
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updated over 16 years ago by johannes

1 replies • 13015 views
Discussion

Path _Delay Command

Category: Logic Design

By Kliatakis
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updated over 16 years ago by Kliatakis

2 replies • 958 views
Discussion

Routing info in Encounter

Category: Logic Design

By Calistudent
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updated over 16 years ago by johannes

1 replies • 12847 views
Discussion

Cadence 6.1.3 libraries

Category: Logic Design

By StreamCX
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updated over 16 years ago by archive

3 replies • 10177 views

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