Mixed-Signal Design

Latest Posts

Discussion

Resistance calculation of switch capacitor circuit

Category: Mixed-Signal Design

By mkza1002
•
updated over 9 years ago by mkza1002

4 replies • 16727 views
Discussion

How can I give Addictive White Gaussian Noise(AWGN) as an INPUT?

Category: Mixed-Signal Design

By Surya Kiran
•
updated over 9 years ago by Andrew Beckett

5 replies • 6308 views
Discussion

Using pPar("") in AMS simulation

Category: Mixed-Signal Design

By designguy
•
updated over 9 years ago by Andrew Beckett

1 replies • 4141 views
Discussion

Verilog-AMS : Incorrect wreal net value of E2R connect module

Category: Mixed-Signal Design

By SimhanAnalog
•
updated over 9 years ago by Andrew Beckett

1 replies • 15067 views
Discussion

Evaluating expression in monte carlo sim

Category: Mixed-Signal Design

By VIPPER
•
updated over 9 years ago by Andrew Beckett

1 replies • 14316 views
Discussion

include function file in verilog-AMS

Category: Mixed-Signal Design

By Narasimhan90
•
updated over 9 years ago by Andrew Beckett

1 replies • 16459 views
Discussion

VPI within analog section

Category: Mixed-Signal Design

By Fabian007
•
updated over 9 years ago by Andrew Beckett

5 replies • 15863 views
Discussion

Difference marker in simvision

Category: Mixed-Signal Design

By SimhanAnalog
•
updated over 9 years ago by SimhanAnalog

2 replies • 20141 views
Discussion

Advice on Efficient and Accurate E2R module

Category: Mixed-Signal Design

By acook
•
started over 9 years ago

0 replies • 13827 views
Discussion

ADEXL measurement for temp drift of an output variable

Category: Mixed-Signal Design

By vamshiky
•
updated over 9 years ago by Andrew Beckett

3 replies • 14110 views
Discussion

Noise analysis for FET transistors

Category: Mixed-Signal Design

By Patrick L
•
updated over 9 years ago by Andrew Beckett

1 replies • 13283 views
Discussion

How to instantiate module ports by name when port bus defined individually - VerilogAMS

Category: Mixed-Signal Design

By SimhanAnalog
•
updated over 9 years ago by Andrew Beckett

1 replies • 3013 views
Discussion

DCO test using Verilog A "unexpected statement "{""

Category: Mixed-Signal Design

By Yizhe Hu
•
updated over 9 years ago by Andrew Beckett

5 replies • 2849 views
Discussion

ncsim with Ultrasim very slow for post layout simulation

Category: Mixed-Signal Design

By dogrush
•
updated over 9 years ago by dogrush

2 replies • 13663 views
Discussion

VHDL-AMS VIEW LIST in ADE

Category: Mixed-Signal Design

By eppo
•
updated over 9 years ago by Andrew Beckett

3 replies • 14838 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.