Mixed-Signal Design

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Discussion

mixed Signal simulation using Analog schematic and VHDL behaviour code

Category: Mixed-Signal Design

By wrensh

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started over 11 years ago

0 replies • 13707 views
Discussion

VerilogA in AMS simulation: string parameter is not properly recognized

Category: Mixed-Signal Design

By jsaenznoval

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updated over 11 years ago by jsaenznoval

2 replies • 15825 views
Discussion

How to use a Hspice model in spectre?

Category: Mixed-Signal Design

By Enycin

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updated over 11 years ago by Enycin

2 replies • 17659 views
Discussion

Using a Design Variable in an input.scs File

Category: Mixed-Signal Design

By Cachi

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updated over 11 years ago by Andrew Beckett

3 replies • 16819 views
Discussion

Switched Cap based System Noise Analysis

Category: Mixed-Signal Design

By Abhishek D

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updated over 11 years ago by Andrew Beckett

7 replies • 19543 views
Discussion

AMS simulation using ADE. How to save internal verilog module signals.

Category: Mixed-Signal Design

By weebey

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started over 11 years ago

0 replies • 15168 views
Discussion

Which simulator is best to use for Mixed-Signal Simulation?

Category: Mixed-Signal Design

By Kabal

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updated over 11 years ago by Andrew Beckett

3 replies • 17906 views
Discussion

Defining a string parameter in a systemverilog model as a design variable

Category: Mixed-Signal Design

By Soner

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updated over 11 years ago by Soner

2 replies • 20504 views
Discussion

AMS simulation with VCD input file

Category: Mixed-Signal Design

By Abhishek D

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updated over 11 years ago by Andrew Beckett

3 replies • 19544 views
Discussion

[Help] How to convert the verilog code to circuit for ADC simulation.

Category: Mixed-Signal Design

By xxgenerall

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updated over 11 years ago by Andrew Beckett

1 replies • 16894 views
Discussion

verilog simulation

Category: Mixed-Signal Design

By sebgimi

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updated over 11 years ago by sebgimi

2 replies • 14595 views
Discussion

Is it possible to have different run modes for different tests in the same ade xl view?

Category: Mixed-Signal Design

By Venkyatcosmic

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updated over 11 years ago by Andrew Beckett

1 replies • 13685 views
Discussion

printing voltages and currents after transient or dc operating point simulations

Category: Mixed-Signal Design

By kawan

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updated over 11 years ago by Andrew Beckett

1 replies • 14466 views
Discussion

Skill function to set "Statistical Variation" in Monte Carlo Sampling

Category: Mixed-Signal Design

By hapn

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updated over 12 years ago by hapn

4 replies • 2074 views
Discussion

An Mixed-Sim(spectreverilog) Error: Component name (cdsNet0) not declared

Category: Mixed-Signal Design

By Lynn Lou

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updated over 12 years ago by Andrew Beckett

3 replies • 1591 views

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