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Mixed-Signal Design

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  • Discussion

    How to use a Hspice model in spectre?

    Category: Mixed-Signal Design

    By Enycin

    •

    updated over 12 years ago by Enycin

    2 replies • 19312 views
  • Discussion

    Using a Design Variable in an input.scs File

    Category: Mixed-Signal Design

    By Cachi

    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 18616 views
  • Discussion

    Switched Cap based System Noise Analysis

    Category: Mixed-Signal Design

    By Abhishek D

    •

    updated over 12 years ago by Andrew Beckett

    7 replies • 21667 views
  • Discussion

    AMS simulation using ADE. How to save internal verilog module signals.

    Category: Mixed-Signal Design

    By weebey

    •

    started over 12 years ago

    0 replies • 16359 views
  • Discussion

    Which simulator is best to use for Mixed-Signal Simulation?

    Category: Mixed-Signal Design

    By Kabal

    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 19909 views
  • Discussion

    Defining a string parameter in a systemverilog model as a design variable

    Category: Mixed-Signal Design

    By Soner

    •

    updated over 12 years ago by Soner

    2 replies • 22124 views
  • Discussion

    AMS simulation with VCD input file

    Category: Mixed-Signal Design

    By Abhishek D

    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 21530 views
  • Discussion

    [Help] How to convert the verilog code to circuit for ADC simulation.

    Category: Mixed-Signal Design

    By xxgenerall

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 18095 views
  • Discussion

    verilog simulation

    Category: Mixed-Signal Design

    By sebgimi

    •

    updated over 12 years ago by sebgimi

    2 replies • 15804 views
  • Discussion

    Is it possible to have different run modes for different tests in the same ade xl view?

    Category: Mixed-Signal Design

    By Venkyatcosmic

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 14823 views
  • Discussion

    printing voltages and currents after transient or dc operating point simulations

    Category: Mixed-Signal Design

    By kawan

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 15592 views
  • Discussion

    Skill function to set "Statistical Variation" in Monte Carlo Sampling

    Category: Mixed-Signal Design

    By hapn

    •

    updated over 12 years ago by hapn

    4 replies • 2593 views
  • Discussion

    An Mixed-Sim(spectreverilog) Error: Component name (cdsNet0) not declared

    Category: Mixed-Signal Design

    By Lynn Lou

    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 2101 views
  • Discussion

    Error in Verilog AMS for decoding logic

    Category: Mixed-Signal Design

    By ksnf3000

    •

    updated over 12 years ago by shalem7

    1 replies • 16025 views
  • Discussion

    How to store the description or the condition of a specification of a design in ADE-XL

    Category: Mixed-Signal Design

    By hapn

    •

    updated over 12 years ago by hapn

    2 replies • 15301 views
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