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Mixed-Signal Design

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  • Discussion

    Error in Verilog AMS for decoding logic

    Category: Mixed-Signal Design

    By ksnf3000

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    updated over 12 years ago by shalem7

    1 replies • 14823 views
  • Discussion

    How to store the description or the condition of a specification of a design in ADE-XL

    Category: Mixed-Signal Design

    By hapn

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    updated over 12 years ago by hapn

    2 replies • 14087 views
  • Discussion

    ncelab: *F,AMSCBINER: Unexpected error encountered

    Category: Mixed-Signal Design

    By beevlsi

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    updated over 12 years ago by Andrew Beckett

    2 replies • 1761 views
  • Discussion

    digital gate delay in AMS design environment

    Category: Mixed-Signal Design

    By apple419

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    updated over 12 years ago by Andrew Beckett

    1 replies • 15328 views
  • Discussion

    regarding photodiode simulation

    Category: Mixed-Signal Design

    By primer

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    started over 12 years ago

    0 replies • 13585 views
  • Discussion

    How to prevent flipping a written text

    Category: Mixed-Signal Design

    By den408nis

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    updated over 12 years ago by Andrew Beckett

    2 replies • 14150 views
  • Discussion

    ploting/saving Verilog-A variables with AMS simulator using Ultrasim Solver

    Category: Mixed-Signal Design

    By aarthymani

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    started over 12 years ago

    0 replies • 1004 views
  • Discussion

    OSCILLATOR DESIGN

    Category: Mixed-Signal Design

    By Sayantan55

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    updated over 12 years ago by Andrew Beckett

    1 replies • 14357 views
  • Discussion

    Ways for assigning/implementing Voltage level(e.g: 1.8/0 V) to binary/logical level(1/0) for Functional Verilog Block used in AMS

    Category: Mixed-Signal Design

    By aarthymani

    $usertype

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    updated over 12 years ago by aarthymani

    2 replies • 2728 views
  • Discussion

    Verilog-AMS Bias Current Modelling

    Category: Mixed-Signal Design

    By shalem7

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    updated over 12 years ago by shalem7

    4 replies • 19434 views
  • Discussion

    saving ams config hierarchy

    Category: Mixed-Signal Design

    By kawan

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    updated over 12 years ago by kawan

    2 replies • 14547 views
  • Discussion

    How to keep connectivity in XL with resistors

    Category: Mixed-Signal Design

    By den408nis

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    updated over 12 years ago by Andrew Beckett

    1 replies • 14438 views
  • Discussion

    can we attach technology file to verilog-AMS design

    Category: Mixed-Signal Design

    By sunilreddy

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    updated over 12 years ago by Andrew Beckett

    1 replies • 13822 views
  • Discussion

    Transient flicker noise simulation

    Category: Mixed-Signal Design

    By Masoud ensaf

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    updated over 12 years ago by Masoud ensaf

    2 replies • 16021 views
  • Discussion

    psl vunit bind to spectre subckt

    Category: Mixed-Signal Design

    By skillseeker

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    started over 12 years ago

    0 replies • 13226 views
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