Mixed-Signal Design

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Discussion

Ways for assigning/implementing Voltage level(e.g: 1.8/0 V) to binary/logical level(1/0) for Functional Verilog Block used in AMS

Category: Mixed-Signal Design

By aarthymani
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updated over 11 years ago by aarthymani

2 replies • 2481 views
Discussion

Verilog-AMS Bias Current Modelling

Category: Mixed-Signal Design

By shalem7
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updated over 12 years ago by shalem7

4 replies • 18344 views
Discussion

saving ams config hierarchy

Category: Mixed-Signal Design

By kawan
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updated over 12 years ago by kawan

2 replies • 13713 views
Discussion

How to keep connectivity in XL with resistors

Category: Mixed-Signal Design

By den408nis
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updated over 12 years ago by Andrew Beckett

1 replies • 13638 views
Discussion

can we attach technology file to verilog-AMS design

Category: Mixed-Signal Design

By sunilreddy
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updated over 12 years ago by Andrew Beckett

1 replies • 13050 views
Discussion

Transient flicker noise simulation

Category: Mixed-Signal Design

By Masoud ensaf
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updated over 12 years ago by Masoud ensaf

2 replies • 15156 views
Discussion

psl vunit bind to spectre subckt

Category: Mixed-Signal Design

By skillseeker
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started over 12 years ago

0 replies • 12559 views
Discussion

controlling the analog solver within verilog

Category: Mixed-Signal Design

By freitas
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started over 12 years ago

0 replies • 12656 views
Discussion

about 64 - 32 bit binaries (ultrasim64)

Category: Mixed-Signal Design

By Thodoros
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updated over 12 years ago by Thodoros

6 replies • 4963 views
Discussion

Designing Digital FIR Filter using Cadence Tools

Category: Mixed-Signal Design

By indra0804
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started over 12 years ago

0 replies • 14338 views
Discussion

Non-piecewise constant argument is detected in the transition filter.

Category: Mixed-Signal Design

By freitas
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updated over 12 years ago by Andrew Beckett

1 replies • 13325 views
Discussion

CADENCE capacitor corners max min typ meaning

Category: Mixed-Signal Design

By Ricardo Alves
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updated over 12 years ago by Andrew Beckett

1 replies • 14231 views
Discussion

NC-Verilog Integration netlister explicitly option

Category: Mixed-Signal Design

By Provence
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updated over 12 years ago by Provence

3 replies • 15889 views
Discussion

Monto carlo simulation

Category: Mixed-Signal Design

By Custom IC Desi
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updated over 12 years ago by Andrew Beckett

1 replies • 13200 views
Discussion

component display

Category: Mixed-Signal Design

By 40Ford
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updated over 12 years ago by Sandeep4386

4 replies • 15431 views

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