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Mixed-Signal Design

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  • Discussion

    ncelab: *F,AMSCBINER: Unexpected error encountered

    Category: Mixed-Signal Design

    By beevlsi

    •

    updated over 12 years ago by Andrew Beckett

    2 replies • 2108 views
  • Discussion

    digital gate delay in AMS design environment

    Category: Mixed-Signal Design

    By apple419

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 16583 views
  • Discussion

    regarding photodiode simulation

    Category: Mixed-Signal Design

    By primer

    •

    started over 12 years ago

    0 replies • 14626 views
  • Discussion

    How to prevent flipping a written text

    Category: Mixed-Signal Design

    By den408nis

    •

    updated over 12 years ago by Andrew Beckett

    2 replies • 15365 views
  • Discussion

    ploting/saving Verilog-A variables with AMS simulator using Ultrasim Solver

    Category: Mixed-Signal Design

    By aarthymani

    •

    started over 12 years ago

    0 replies • 1180 views
  • Discussion

    OSCILLATOR DESIGN

    Category: Mixed-Signal Design

    By Sayantan55

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 15511 views
  • Discussion

    Ways for assigning/implementing Voltage level(e.g: 1.8/0 V) to binary/logical level(1/0) for Functional Verilog Block used in AMS

    Category: Mixed-Signal Design

    By aarthymani

    •

    updated over 12 years ago by aarthymani

    2 replies • 3168 views
  • Discussion

    Verilog-AMS Bias Current Modelling

    Category: Mixed-Signal Design

    By shalem7

    •

    updated over 12 years ago by shalem7

    4 replies • 21079 views
  • Discussion

    saving ams config hierarchy

    Category: Mixed-Signal Design

    By kawan

    •

    updated over 12 years ago by kawan

    2 replies • 15789 views
  • Discussion

    How to keep connectivity in XL with resistors

    Category: Mixed-Signal Design

    By den408nis

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 15561 views
  • Discussion

    can we attach technology file to verilog-AMS design

    Category: Mixed-Signal Design

    By sunilreddy

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 14923 views
  • Discussion

    Transient flicker noise simulation

    Category: Mixed-Signal Design

    By Masoud ensaf

    •

    updated over 13 years ago by Masoud ensaf

    2 replies • 17490 views
  • Discussion

    psl vunit bind to spectre subckt

    Category: Mixed-Signal Design

    By skillseeker

    •

    started over 13 years ago

    0 replies • 14200 views
  • Discussion

    controlling the analog solver within verilog

    Category: Mixed-Signal Design

    By freitas

    •

    started over 13 years ago

    0 replies • 14321 views
  • Discussion

    about 64 - 32 bit binaries (ultrasim64)

    Category: Mixed-Signal Design

    By Thodoros

    •

    updated over 13 years ago by Thodoros

    6 replies • 6418 views
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