• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      Charlie
      Charlie 110 Points
    • 2
      eDave
      eDave 70 Points
    • 3
      oldmouldy
      oldmouldy 55 Points
    • 4
      ShawnLogan
      ShawnLogan 50 Points
    • 5
      steve
      steve 45 Points
  • Leaderboard

    • 1
      steve
      steve 17,769 Points
    • 2
      oldmouldy
      oldmouldy 13,695 Points
    • 3
      eDave
      eDave 10,331 Points
    • 4
      ShawnLogan
      ShawnLogan 9,710 Points
    • 5
      skillUser
      skillUser 7,498 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    export snp s parameter from multiple conditions in ADE explorer

    Category: Custom IC Design

    By Jay Yang

    •

    started over 5 years ago

    0 replies • 12908 views
  • Discussion

    Copy Net class from Physical to Electrical

    Category: Allegro X PCB Editor

    By Lennie

    •

    updated over 5 years ago by Lennie

    8 replies • 16843 views
  • Discussion

    well tested 0201 symbol footprint

    Category: Allegro X PCB Editor

    By frank mpbc

    •

    updated over 5 years ago by frank mpbc

    12 replies • 21900 views
  • Discussion

    Constraint set up for delta and tolerance

    Category: Allegro X PCB Editor

    By jemarods

    •

    updated over 5 years ago by LouShay

    9 replies • 21890 views
  • Discussion

    Different results between PSS and Transient Simulation when using NPORT (EMX)

    Category: Custom IC Design

    By youckgab

    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 15908 views
  • Discussion

    How to keep the cline segment when they touch the same net via?

    Category: PCB Design

    By ichliebedich

    •

    updated over 5 years ago by excellon1

    1 replies • 14094 views
  • Discussion

    Clock tree synthesis error using innovus

    Category: Digital Implementation

    By Biasing

    •

    started over 5 years ago

    0 replies • 17774 views
  • Discussion

    Allegro 17.2 change padstack in .dra symbol

    Category: Allegro X PCB Editor

    By frank mpbc

    •

    updated over 5 years ago by masamasa

    2 replies • 13304 views
  • Discussion

    Annotation does not work however, Print DC operating point works fine - ISSUE

    Category: Custom IC Design

    By FormerMember

    •

    updated over 5 years ago by Avinash Murugesan

    6 replies • 8528 views
  • Discussion

    Re: Extracting device Vgb,Vsb,Vdb info from 'tranOp ??

    Category: Custom IC Design

    By npamd

    •

    updated over 5 years ago by Andrew Beckett

    8 replies • 4621 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information