• Discussion

  modify the font size in virtuoso Locked

  8209 views
  1 reply
  Latest over 1 year ago
  by RobMan
• Discussion

  Replacing the part in the design with another part.

  2830 views
  0 replies
  Started over 1 year ago
  by yugandhar
• Answered

  Changing Wire Property Name from Port Name to Wire Aliasname +1

  1612 views
  2 replies
  Latest over 1 year ago
  by karthikeyank
• Discussion

  How to do pin swapping in OrCAD X Presto

  1054 views
  0 replies
  Started over 1 year ago
  by mahimag
• Discussion

  Explorer to run an AMS simulation by copying the files rather than using their absolute path Locked

  4177 views
  0 replies
  Started over 1 year ago
  by Pedro P
• Discussion

  xmelab: *E,CUVHNF error using Xcelium 19.09-s008 Locked

  4105 views
  4 replies
  Latest over 1 year ago
  by markris
• Discussion

  Generating and importing MDIF File in AWR22.1

  4992 views
  0 replies
  Started over 1 year ago
  by SimTech
• Discussion

  Deepprobe within systemverilog hierarchy Locked

  7865 views
  7 replies
  Latest over 1 year ago
  by NewScreenName
• Discussion

  Create schematic from netlist(verilog) Locked

  2292 views
  2 replies
  Latest over 1 year ago
  by SimhanAnalog
• Discussion

  floating metals and vias Locked

  4133 views
  0 replies
  Started over 1 year ago
  by nen28
• Not Answered

  How to convert IBIS Models into PSpice Model ? 0

  17794 views
  6 replies
  Latest over 1 year ago
  by EMIsleuth
• Discussion

  Export layout from Layout XL Locked

  5931 views
  5 replies
  Latest over 1 year ago
  by Andrew Beckett
• Discussion

  Re: evaluating of variables in netlist created by maeCreateNetlistForCorner Locked

  4173 views
  1 reply
  Latest over 1 year ago
  by Andrew Beckett
• Discussion

  ViVA- set different color to each psf Locked

  995 views
  2 replies
  Latest over 1 year ago
  by Andrew Beckett
• Discussion

  Pop Up Messages Locked

  4904 views
  3 replies
  Latest over 1 year ago
  by Andrew Beckett