• Discussion

  Out of practice. Blind-Buried Vias in Allegro L. Locked

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  2 replies
  Latest over 14 years ago
  by Robert Finley
• Discussion

  RTL Compiler: write_sdf and clocks Locked

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  3 replies
  Latest over 14 years ago
  by mclarke
• Discussion

  mapping symbol list to a value list Locked

  15120 views
  3 replies
  Latest over 14 years ago
  by Andrew Beckett
• Discussion

  Equivalent of leIsContact in IC6 Locked

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  2 replies
  Latest over 14 years ago
  by cessej
• Discussion

  Pin order of a PMOS in layout cannot match with schematic Locked

  16987 views
  2 replies
  Latest over 14 years ago
  by naderi
• Discussion

  How do I compare 2 schematic cellViews using skill (SVS) - code example.... ? Locked

  2936 views
  1 reply
  Latest over 14 years ago
  by Quek
• Discussion

  how can i increase the width of pmos upto 873.6um Locked

  14163 views
  2 replies
  Latest over 14 years ago
  by 1234v
• Discussion

  How to change output signals prior simulation in the batch mode Locked

  13106 views
  0 replies
  Started over 14 years ago
  by Vitaly Rubin
• Discussion

  can we define some component's parameter as a design variable by skill function? Locked

  1304 views
  1 reply
  Latest over 14 years ago
  by Quek
• Discussion

  Cadence PCB Panelling Locked

  14348 views
  6 replies
  Latest over 14 years ago
  by Ark angel
• Discussion

  How to mask-out all but a highlighted net, component, pin, etc? Locked

  14744 views
  2 replies
  Latest over 14 years ago
  by kidder03
• Discussion

  REG:SOLDEMASK OPENING OF PTH VIA'S Locked

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  2 replies
  Latest over 14 years ago
  by Mstrghettorigg
• Discussion

  Sollution for making PCB Panel Locked

  13399 views
  4 replies
  Latest over 14 years ago
  by Ark angel
• Discussion

  orcad 16.3 Locked

  13149 views
  1 reply
  Latest over 14 years ago
  by oldmouldy
• Discussion

  Is there any faster way to get hierarhically tree report? Locked

  16820 views
  6 replies
  Latest over 14 years ago
  by kbhow