• Discussion

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  16914 views
  3 replies
  Latest over 15 years ago
  by Rik Lee
• Discussion

  explenation on the verilog_wire() method Locked

  14072 views
  2 replies
  Latest over 15 years ago
  by sgor
• Discussion

  No pull down with right mouse click in PCB Designer. Locked

  13867 views
  4 replies
  Latest over 15 years ago
  by hfs440
• Discussion

  Help me change master for schematic view Locked

  16978 views
  3 replies
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  Cadence, shortened net, global pins Locked

  6548 views
  2 replies
  Latest over 15 years ago
  by StreamCX
• Discussion

  problem in running IC610 (CADENCE),showing skill errors Locked

  7760 views
  9 replies
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  Capture deleting part properties (wrong forum perhaps) Locked

  16072 views
  5 replies
  Latest over 15 years ago
  by redwire
• Discussion

  System Verilog with Spice *F,INTERR - cu_check_port_var_aca Locked

  1255 views
  1 reply
  Latest over 15 years ago
  by StephenH
• Discussion

  Testbench with non-unique module names in sub-blocks Locked

  17786 views
  2 replies
  Latest over 15 years ago
  by StephenH
• Discussion

  Error importing netlist in allegro 16.3 Locked

  13124 views
  2 replies
  Latest over 15 years ago
  by ELEKVN
• Discussion

  Working with Global Route Environment Locked

  12618 views
  0 replies
  Started over 15 years ago
  by ELEKVN
• Discussion

  Physical constraint error Locked

  13544 views
  3 replies
  Latest over 15 years ago
  by Ejlersen
• Discussion

  Untouchable track Locked

  12984 views
  1 reply
  Latest over 15 years ago
  by stellar
• Discussion

  Who wants a free, cross-probing viewer for DEHDL and PCB Editor? Locked

  15738 views
  6 replies
  Latest over 15 years ago
  by Boardman
• Discussion

  Need advice in cleanup effort in OrCAD 16.3 Locked

  13768 views
  1 reply
  Latest over 15 years ago
  by Ejlersen