• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Suggested Answer

    Unable to create bus in OrCAD capture in hierarchical design unless schematic is root schematic 0

    6790 views
    2 replies
    Latest over 2 years ago
    by rg13
  • Not Answered

    On Cloud Losses Simulation Data 0

    6215 views
    2 replies
    Latest over 2 years ago
    by OscPn
  • Discussion

    SystemVerilog: Assign a array to a bus Locked

    10904 views
    3 replies
    Latest over 2 years ago
    by tpylant
  • Suggested Answer

    RefDes Duplication 0

    6220 views
    2 replies
    Latest over 2 years ago
    by rg13
  • Discussion

    Innovus: Placement of Bond Pads Locked

    8887 views
    0 replies
    Started over 2 years ago
    by Anas2023a95
  • Discussion

    Innovus: Routing Quires & General Advice Locked

    7174 views
    3 replies
    Latest over 2 years ago
    by Anas2023a95
  • Suggested Answer

    Schematic Symbol Color Fill? 0

    6507 views
    1 reply
    Latest over 2 years ago
    by AyushD
  • Discussion

    How to extract the junction capacitor in pmos capacitor?? Locked

    9109 views
    3 replies
    Latest over 2 years ago
    by Guangjun Cao
  • Discussion

    Variable Parameters in Fluid Pcell Locked

    8143 views
    3 replies
    Latest over 2 years ago
    by Andrew Beckett
  • Discussion

    Differences between Verilog, Verilog-A, Verilog-AMS and SystemVerilog Locked

    29383 views
    2 replies
    Latest over 2 years ago
    by HoWei
  • Discussion

    Windows/ Mac compatibility for Cadence softwares Locked

    14220 views
    1 reply
    Latest over 2 years ago
    by StephenH
  • Discussion

    placement of multiple elements using a file that contains the coordinates Locked

    7521 views
    2 replies
    Latest over 2 years ago
    by ArantxaU
  • Discussion

    Error in Running the simulation Locked

    8027 views
    1 reply
    Latest over 2 years ago
    by ShawnLogan
  • Discussion

    Is it possible to do transient simulation with and without transient noise in one go? Locked

    8152 views
    4 replies
    Latest over 2 years ago
    by delgsy
  • Discussion

    How should I use skill code to get the mapping between instanceName and its terminalName and netName Locked

    7203 views
    1 reply
    Latest over 2 years ago
    by AurelBuche
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information