• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    Why to use Allegro System Capture – Version Control

    9312 views
    3 replies
    Latest over 3 years ago
    by Schulz Jordan
  • Discussion

    [INNOVUS] Performing top level implementation for hierarchal/block IC design ("Bottom Up" approach) Locked

    6431 views
    2 replies
    Latest over 3 years ago
    by henny123
  • Discussion

    How to get windowID of Skill IDE? Locked

    8844 views
    2 replies
    Latest over 3 years ago
    by Kevin Li
  • Discussion

    Copy and Paste Selected Objects While Rotating In Place Locked

    8905 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    Retaining group membership when copying fig group objects with "Transparent Group" set to "ON" Locked

    1498 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Not Answered

    Etch Length By Pin Pair Report includes pin_delay(s) 0

    1438 views
    0 replies
    Started over 3 years ago
    by SyraG
  • Discussion

    HOW TO CALCULATE CLOCK FREQUENCY OF VPWL VOLTAGE SOURCE Locked

    8576 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Not Answered

    Edit: Solved. (Reversing mouse wheel zoom direction setting gets erased.) 0

    8720 views
    0 replies
    Started over 3 years ago
    by j22987
  • Discussion

    How to get the object id of deleted instance, net, wire or anything? Locked

    11364 views
    8 replies
    Latest over 3 years ago
    by Purbayan
  • Discussion

    Ignoring instances in the layout during LVS (and/or DRC) Locked

    6435 views
    4 replies
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    Importance of Package parasitics of a buffer model in TopXp PBA and SLA analyses

    7460 views
    0 replies
    Started over 3 years ago
    by SimTech
  • Not Answered

    I can't find the problem of this circuit - sbreak, wbreak, ERROR(ORPSIM-16367): End of expression not seen 0

    2659 views
    2 replies
    Latest over 3 years ago
    by Schulz Jordan
  • Discussion

    Why to use Allegro System Capture – Smart PDF

    9219 views
    2 replies
    Latest over 3 years ago
    by atishcdns
  • Not Answered

    I cannot open 17.4 BRD files on a 17.4 install 0

    10243 views
    2 replies
    Latest over 3 years ago
    by SOT23
  • Discussion

    AMS simulation fails to generate netlist Locked

    13778 views
    9 replies
    Latest over 3 years ago
    by Yongqi Hu
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information