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Forum - Thread List
  • Suggested Answer

    Correct use of GLAPLACE, ELAPLACE, or LAPLACE elements 0

    803 views
    1 reply
    Latest 9 months ago
    by rg13
  • Suggested Answer

    Exporting Layout Views as SVG Using SKILL in Allegro 0

    2379 views
    4 replies
    Latest 9 months ago
    by eDave
  • Not Answered

    Orcad X Capture CIS (23.1) location of visible properties change if I rotate schematic symbol 0

    830 views
    1 reply
    Latest 9 months ago
    by andakConsultingLtd
  • Discussion

    Netlisting error Locked

    3942 views
    0 replies
    Started 9 months ago
    by PE202503078250
  • Discussion

    how to find most common element from list Locked

    2464 views
    1 reply
    Latest 9 months ago
    by AaronSymko
  • Discussion

    import verilog Locked

    2855 views
    1 reply
    Latest 9 months ago
    by MS202504187741
  • Not Answered

    TCL foreach command encryption issue? 0

    1459 views
    2 replies
    Latest 9 months ago
    by palemoon
  • Discussion

    Error during DC Annotation and DC IV Curve plotting

    6960 views
    6 replies
    Latest 9 months ago
    by Dr Pournamy
  • Discussion

    Looking for SKILL or Bindkey to change wire width based on list of width while doing wire command Locked

    4410 views
    7 replies
    Latest 9 months ago
    by Finn Huckle
  • Discussion

    ERROR (SFE-874). Not able to resolve this issue Locked

    3146 views
    2 replies
    Latest 9 months ago
    by akaraguppi
  • Discussion

    Importing Synopsys .slib symbols to Cadence Virtuoso Locked

    2799 views
    2 replies
    Latest 9 months ago
    by rajasnene16
  • Discussion

    Conditional Bindkey Function Locked

    2915 views
    2 replies
    Latest 9 months ago
    by Andrew Beckett
  • Discussion

    PCell CDF parameters are not preserved Locked

    2520 views
    0 replies
    Started 9 months ago
    by Naveen002
  • Suggested Answer

    capture cis 24.1 crash upppon creating new project/design 0

    1618 views
    3 replies
    Latest 9 months ago
    by Akshay khosla
  • Discussion

    Glitch in Synthesized Netlist Simulation of SR Latch — Occurs Only in One Instance Locked

    3228 views
    0 replies
    Started 9 months ago
    by SaranyaBalan
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