• Discussion

  Support VHDL2008 in ncsim Locked

  15909 views
  2 replies
  Latest over 6 years ago
  by pyohayo
• Discussion

  create a pcell ( symbol, not layout), and create its cdf. Locked

  17259 views
  3 replies
  Latest over 6 years ago
  by Andrew Beckett
• Discussion

  VIVA calculator dnl&inl Locked

  3761 views
  3 replies
  Latest over 6 years ago
  by Andrew Beckett
• Discussion

  converting a text into a polyline on dxf export Locked

  19243 views
  8 replies
  Latest over 6 years ago
  by DavidJHutchins
• Discussion

  3D Via modeling Locked

  13133 views
  0 replies
  Started over 6 years ago
  by shraws
• Discussion

  Setting up Constraint Manager to detect unwanted stubs Locked

  13832 views
  1 reply
  Latest over 6 years ago
  by Wild
• Discussion

  Converting a veriloga model to a schematic symbol Locked

  15781 views
  4 replies
  Latest over 6 years ago
  by lbodepu
• Discussion

  How to rename all instances in layout to match schematic Locked

  17327 views
  1 reply
  Latest over 6 years ago
  by Andrew Beckett
• Discussion

  Change via net connectivity Locked

  14845 views
  1 reply
  Latest over 6 years ago
  by Andrew Beckett
• Discussion

  "Transient Operating Points" can't be annotated after "tran" simulation Locked

  6842 views
  5 replies
  Latest over 6 years ago
  by DavidLou
• Discussion

  Design Entry HDL 16.6 Locked

  13128 views
  0 replies
  Started over 6 years ago
  by layoutguy
• Discussion

  what is making the suffix number of the name of the wire? Locked

  16522 views
  5 replies
  Latest over 6 years ago
  by johnthanchau
• Discussion

  Transient simulation crashes SPECTRE181, APS Locked

  16819 views
  2 replies
  Latest over 6 years ago
  by Michael H
• Discussion

  CRefer in Allegro System Architect Locked

  13770 views
  0 replies
  Started over 6 years ago
  by akmo25
• Discussion

  Cut Segment

  10583 views
  3 replies
  Latest over 6 years ago
  by ENEGUE