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In this week's Whiteboard Wednesdays video, Pushkar Patwardhan gives an overview of the instruction set architecture (ISA) and features of the Tensilica Fusion G6 DSP, a new DSP in the Fusion G DSP Family. He compares the features of the Fusion G3 and G6 DSPs, showing the increased capabilities and performance of the Fusion G6 DSP. After describing the typical radar processing pipeline, he outlines the features of the…

Every CDNLive has a little bit of a different structure. At CDNLive EMEA in Munich, we start with Monday lunch, giving people the opportunity to fly in from other parts of Europe. The first day is has presentations, some by Cadence but mostly by customers...

Hello Spectre Users,

Simulating S-parameters in a time domain (transient, periodic steady state) simulator has been and continues to be a challenge for many analog and RF designers.

I'm often asked:

• What is required in order to achieve accurate...

When I was on my last tour of duty at Cadence in the early 2000s, we had a late afternoon seminar series. One of the speakers was Edsger Dijkstra. He was a legend in computer science, one of the pioneers of many important aspects of programming. Perhaps...

Only last week, in Are General-Purpose Microprocessors Over? I wrote about how general-purpose processors are never going to get any faster and so the system architecture of the future will consist of a general-purpose processor (probably multicore) along...

I went to the annual SOI Silicon Valley Symposium recently. As last year, they had to close registration because the room was full. To see what I wrote last year, see FD-SOI: Is It Really a Thing? and like last year, that was the big question. It is like...

It's been a while since analogLib was updated, so we decided to pay some attention to some long standing and popular requests in the recent ISRs!

In IC6.1.7 ISR6, the ability to use parameterization for the s-param file in the nport instance was added. This provides the flexibility to create the s-param file as a design variable in your simulation test setup. You can very simply…

The 6th RISC-V workshop was held in early May. It was the first one in Asia, at Shanghai Jiao Tong University and was co-sponsored by the University and by NVIDIA.

Why NVIDIA? Partly because they have a sizable Shanghai office. But as I wrote last year...

https://youtu.be/WTQhUyl2BBE

Coming from Jing'an Park, Shanghai, China (camera Hongkai Guo)

Monday: CDNLive Tensilica Announcement

Tuesday: CDNLive Munich Press Conference

Wednesday: CDNLive Munich 1

Thursday: CDNLive Munich 2

Friday: DreamChip...

There is apparently a rule of thumb among journalists that when the headline of an article asks a yes/no question, the answer is always 'no'. Well, of course microprocessors are not over, so the answer follows the rule. But improvements in general-purpose...

In this week's Whiteboard Wednesdays video, Megha Daga takes a deep dive into compute requirements, one of the biggest challenges in Convolutional Neural Networks (CNNs) and some ideas on how to handle them.

www.youtube.com/watch

Space turns out to be an interesting area for semiconductors, especially looking at the soft error rate (SER), which are glitches, known as single event effects (SEE) or single event upsets (SEU), caused by atomic particles that can flip a bit in memory...

The keynote at the IRPS reliability conference I attended was by Nancy Currie-Gregg. Today she works at the NASA Engineering and Safety Center, but she has been on four space shuttle missions to Hubble and the International Space Station, in 1993, 1995...

One presentation at the recent CDNLive Silicon Valley was about using Cadence tools to design products on TSMC's N7 process (7nm). It was standing room only, even after moving to a bigger room. The focus of the presentation was on the digital flow and...

Indeed, the new Expression Builder has made expression creation much easier, but are you still wishing for some more enhancements and handy features available right under it? Would it make working with expressions much quicker and easier if you have an option to evaluate or plot them from within the Expression Builder, just like the way you do with the Calculator. So, here your wish comes true with the new evaluation…

UVM, the Universal Verification Methodology, just became IEEE 1800.2-2017. I wondered if that was significant or not, and I knew just the person to ask. Not only that, his office is about ten feet from mine.

Cadence had to work long and hard to find...

https://youtu.be/sIFo4JKjVxw

Coming from NASA Ames Research Center, Sunnyvale (camera Sean)

Monday: NASA: "Never have another accident due to our organizational flaws."

Tuesday: Soft Error Rate in Satellites and Cars

Wednesday: Are General...

Yes, it's true. After attending CDNLive EMEA for the last couple of years, Bayern München will not be there this year. Real Madrid eliminated them from the Champions League on April 18 (it was close, the game went to extra time). This isn't as silly as...

In this week's Whiteboard Wednesdays video, Pulin Desai describes the main features of the Vision C5 DSP, the first standalone Neural Network DSP IP, and how it is positioned with the rest of the Vision DSP offering.

www.youtube.com/watch

Scott Barric of MicroSemi is one of the people who have been using the pre-release version of Pegasus, the new physical verification solution that Cadence announced at CDNLive Silicon Valley. See Pegasus Flies to the Clouds for more details.

Microsemi...

So you have your RTL written, and it’s time to optimize to reduce power. If that’s your plan, you are likely leaving power on the table. It’s not that you can’t get a lot of savings with existing RTL synthesis tools (you certainly can!), but the biggest bang for the buck comes from early design decisions.

Next time… start sooner!

In fact, experts (not me, real experts) estimate that optimal…

It’s been quite a while since I wrote about “Things I Learned by Browsing Cadence Online Support”.  That absolutely does not mean that I haven’t learned anything recently by browsing Cadence Online Support.  It just means I haven’t had time to write about it!

So now it’s time to expand and re-purpose the “Virtuosity” brand.  From now on, the blogs under that heading will…

I pointed out recently that although La La Land is a romance, the movie opens with cars. The semiconductor industry is like that, too—no matter which way you turn it is automotive. It may not show yet in manufacturing volume and revenue, since it is...

In this week's Whiteboard Wednesdays video, Tom Hackett traces the evolution of the von Neumann computer architecture through a series of adaptations intended to bypass processing bottlenecks that appeared as more and more demands were placed on computing systems.  This provides a historical lens with which to view the recent development of the CCIX interconnect standard.

www.youtube.com/watch