Community

https://youtu.be/IAPCDXodsno

Monday: James Adams of the Raspberry Pi foundation talks about how Cadence PCB tools were used to design the Raspberry Pi

Tuesday: At the recent RISC-V workshop, SiFive announced the first commercially available RISC-V ...

At EDPS back in May (yes, I know I'm behind), Andrew Filo talked about Building the Internet of Space (IOS). He is an independent consultant but works with places like NASA Ames and was a consultant on the 3D printer in the ISS. What he was really...

Some things are best described with tables—each column shows the values for one category, and each row encapsulates one given set of values for all categories. e verification language code is a perfect fit.

This blog describes how to use tables in your verification environment code to make the code more readable and more easily maintained. The tables can be written in the code or they can be pulled in from an external…

I attended a recent workshop on Protium titled Accelerating Embedded Software Development: Protium—Ease of Use in FPGA-Based Prototyping. By the way, Protium really is a word, used in chemistry and physics when they need to specify the isotope of...

Tired of struggling with pairing your Bluetooth devices and getting them to work with each other? In this week’s Whiteboard Wednesdays video, Scott Jacobson explains how Bluetooth 5 does away with this and other range limitation problems and makes connecting your mobile devices seamless.

https://youtu.be/qEA9OYRifWo

There is an Accellera working group that is developing a portable stimulus standard. Like any Accellera group, it contains vendors and users so that both communities are represented.The working group is chaired by Faris Khundakjie of Intel, the vice-chair...

Soon it is the International Electron Devices Meeting. It takes place in San Francisco Hilton Union Square (which is actually not in Union Square but on O'Farrell Street a couple of blocks away). It is from December 3rd to 7th. So it starts next weekend...

https://youtu.be/CUGTiPJQjuI

Monday: My preview of IEDM which includes 7nm from TSMC and from GF/Samsung/IBM

Tuesday: The portable stimulus standard (PSS), which Cadence is deeply involved with

Wednesday: Protium, Cadence's FGPA prototyping...

It’s Thanksgiving! Happy Thanksgiving if you are reading this on the day. Cadence is closed, of course. But here is a post anyway. This has nothing to do with EDA or the semiconductor ecosystem or even Cadence. It is also a puzzle and an important lesson...

Have you ever come across a situation where you have a test setup in ADE Explorer and you need to create similar setups with slight variations and then save them in different cellviews? 

Before starting with this task, the first thing that strikes anyone’s mind is to find out a way that can help avoid hassles of doing the same task again and again. 

Virtuoso ADE Explorer brings to you the ability to save the current…

Allegro PCB Editor now offers Rigid-Flex applications where it’s common to have different fabrics across the final PCB product. The new functionality offers integrating more technology into less material space. This technology enables design flexibility way beyond conventional rigid interconnect methods. Rigid-flex consists of flex circuit(s) that are laminated within a rigid dielectric material. Base Material for flex…

There was a recent panel discussion at Cadence on the future of EDA. The panelists all got to have their say first. You can read about that in the last two days' blog posts: The Future of EDA: The View from Academia and Future of EDA: Industry, Well...

There was a recent panel discussion at Cadence on the future of EDA. If you didn't see it, then read yesterday's post first, which introduces everyone and has the view from academia: The Future of EDA: The View from Academia.

There was a recent panel discussion at Cadence on the future of EDA. Of course the E in EDA stands for electronics, but that's far too boring in the IoT era, so everyone called it the "cyber-physical" domain. To be fair, that fitted with the academics...

Via transitions are very common for signals. And in high speed frequencies, these via transitions can be a major contributor to signal degradation in PCB interconnects. High speed channels require ground via(s) close to critical signals to reduce loss of signal integrity by providing continuous return current path when signals transition layers.

If you are a PCB design engineer, you know very well that layout implementation…

The 5th RISC-V workshop is coming up on November 29 and 30 on the Google Quad campus (468 Ellis Street, Mountain View, CA). RISC-V is pronounced "risk five", so perhaps we should just call it the Vth workshop. The preliminary schedule has now been published...

https://youtu.be/dHvlzjjH9SA

Monday: The Academic Panel: the Academics Go First

Tuesday: The Academic Panel: the Cadence execs respond

Wednesday: Audience Q&A

Thursday: You'll have to look to find out...oh, and Happy Thanksgiving

Friday...

At the largest gathering of formal verification (FV) engineers in the world, also known as the Jasper User Group, Ziyad Hanna gave the final presentation. Since this was on future developments in the Jasper product line, and since he is the VP of R&D...

After ARM on the first day, the keynote on the second day of DVCon was by NXP. For semiconductor, automotive is still much smaller than mobile, but it is growing fast. It is growing not so much because of inherent growth in the underlying market for cars...

In this week's Whiteboard Wednesdays video, Moshik Rubin takes a closer look at the popularity of CSI2, DSI, and other common MIPI protocols.

www.youtube.com/watch

The first ARM is the ARM we all know, Advanced RISC Machines (the A originally stood for Acorn but that story is for another day). The second ARM stands for "Architecture Reference Manual". At the Jasper User Group recently, Daryl Stewart of ARM's technology...

Jon Masters is in an odd position—he is the chief ARM architect at Red Hat. Since Red Hat must make almost all of its money from selling operating systems and services for x86-based servers, this is definitely a minority interest position. However, he...

Improve Route Channel Utilization with Tabbed Routing

Tabbed routing is a new method in which trapezoidal shapes called tabs are added to parallel traces to control impedance in the pin field/breakout regions, and reduce crosstalk in open field regions. It is a breakthrough routing strategy that allows for longer trace lengths and more compressed routing.

Unfortunately, this new routing technology increases layout…