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Do you wish you could lock specific aspects of a DEHDL design content? Do you need to standardize on color used for parts, wires, text, etc. in a design? Do you wish designers would maintain a standard grid?

Well - all this (and more!) can be accomplished through the project .cpm file directive locking capabilities available since the SPB16.0 release. I'm writing about this since there are still some customers I interact…

I arrived safe and sound at the Embedded Systems Conference in Boston today. It's been a few years since I have attended ESC, but it all came back to me quickly, and is just as I remember it, a lot of small booths with vendors showing small boards doing something (hopefully something interesting and not something small).

The most interesting talk I attended was Virtualization for Embedded and Real-Time Systems. Virtualization…

The question of how to integrate legacy VMM VIP into OVM verification environments is an issue on the minds of many in the verification ecosystem.  Ed Sperling has written a good article on this subject.

For folks who have been tracking progress on the Accellera VIP TSC reflector, or in the meetings directly, it appears that progress is being made.  Of course, that progress is possible in part because the OVM has been available…

Apologies for the shameless promotion, but I can't resist touting an event I'm producing next Tuesday: an "Advanced Verification Techtorial" on the Cadence San Jose campus.  Here is the detailed agenda:
http://www.secure-register.net/flyer.php?id=260 

If you are the Silicon Valley area next Tuesday (10/28), by all means sign-up and come by:
http://www.secure-register.net/cadence.php?product=3

More on techtorials…

 Most of my experience in functional verification prior to my dabbling in FPV was in the area of SystemC/SCV and simulation acceleration. I naturally brought a simulation-mindset to FPV. As a matter of fact, it is possible to go far in FPV by thinking about the verification problem in procedural terms. Instead of writing BFMs and behavioral checkers, you write properties that each model a small portion of the environment…

It is not too late to sign up for the Package Power Integrity webinar that will be presented on 10/23 11:00 PDT.  Click here to register.

This webinar will give you a heads-up on new (SPB 16.2) features in the package / SiP SI tools that can be used to analyze the package power delivery network (PDN).  Attendees will learn the methodology for validating power delivery by analyzing impedance of the PDN. You'll also learn…

Before getting into the details of today's topic I'm happy to report a brand new baby girl was born on October 1 into the Andrews family of Ham Lake, MN. She is our sixth child, and the forth girl to go along with two boys. Currently, I play a lot of golf with my oldest three kids and with the new baby girl I'm assured the three youngest will form my next foursome after the oldest three grow up and leave home…

 If you've been checking out the other blogs here in the Digital Implementation community, you've probably seen mention of the database access mechanism dbGet/dbSet. Back in the SoC-Encounter 6.x days, our very own BobD gave me a quick demo of dbGet. I couldn't wait for 7.1 to come out, so I could start using it. Of course I got busy with customer projects and never quite found the time to play with it and get…

My first post served as a context for this blog. It also telegraphed my intention to set down a few reasons for the initial difficulties faced by long-time simulation users, specifically verification engineers, in applying formal property verification (FPV). Here is my Top-5 list in no particular order.

1. Procedural Versus Declarative Expression Of Intent

Simulation languages like Verilog, SystemC, e and the rest are procedural…

Today's announcement on our expanding Verification IP (VIP) portfolio inspired me to interview my colleague Dave Tokic to elaborate on this news.  Enjoy the video!

So who is Thad McCracken and why should you be interesting in reading this blog entry?  Thad has been a Cadence Core Comp Senior Technical Leader focused on the Encounter Platform for 6 years(essentially a specialized Applications Engineer that bridges the gap between the field and R&D.)  I sometimes refer to him as “The President and CEO of McCracken Labs” because he has been responsible for some very popular innovations…

In my last post, I talked about how OVM is a methodology for building automated e or SystemVerilog testbenches for Metric Driven Verification (MDV).  As it turns out, one of my colleagues, John Nehls from our Verification Core Comp organization, just wrote an article along similar lines, where he goes into a bit more detail, so rather than repeating what he said, I highly recommend reading his article.

As John points out…

Today, a friend sent me a link to an article on embedded.com that talks about my upcoming presentation at the Embedded Systems Boston Conference. I love the title about turning hardware and software design upside down. I guess it's true that this is what I have been doing for some time.

The unique thing about it was that was the first time I could remember where an article appeared in a publication or on the web that…

Yes, I'm asking about chips that will have 1 billion -- that's billion with a "B" -- logic gates (implying they will have ~6 billion transistors).  Last year I only heard of one such chip in the works anywhere, but just this past month in the course of my travels I received word of two more such massive devices on the drawing board.  Furthermore, judging by the careful silence of some members of the "ClubT…

Hi Everyone!

Welcome to my first blog post! My plan for this space is to share with you various tips and tricks in SoC-Encounter as well as new things I learn along the way. I use Encounter every day as part of my job in Cadence Design Services. Knowledge is a two-way street, so I'm hoping that we'll have some good comments revealing how you, the customers, are using Encounter as well. Now, on to business!

My team…

In the SPB16.01 release, for the Constraint Manager in DEHDL, the is a new scope of "Class" for Match Groups.

This new scope will utilize the “Net Class” signal grouping introduced in 16.0, and allow users to mimic the capability of Bus Scope with this new arbitrary grouping. It will operate as Bus Scope does today, i.e. it is limited to ECSets, and is only used during the ECSet mapping process, creating distinct…

This year, Cadence increases its focus on system-level design and verification events. During the latest CDNLive San-Jose that was held in September, the guest keynote - Dr. Jan Rabaey, Distinguished Professor of Electrical Engineering at the University of California, Berkeley, described the challenges and opportunities facing customers and partners in the years ahead.

System-level design was the center of his talk. According…

Several years ago, I have purchased a cell phone with a 2 years contract from one of the major wireless service providers in the US. The battery lifetime between charges of this phone was terrible - 24 hours. The service provider promised me that there will be a firmware upgrade which will improve the battery charge time. 9 months later, I uploaded new firmware which allowed me to double the time between charges. These kind…

Global Timing Debug has been a very popular capability within SoC-Encounter.  Once you start using it, it becomes hard to go back to looking at text reports.  The high level philosophy of Global Timing Debug is to assess not just the worst path in the design- but all of the failing paths to get a feel for the categories of problems which are blocking timing closure.

That said, I find that Global Timing Debug visualizes a…

There is a definite challenge in maintaining productivity when it comes to realizing a design.  Anything that helps the layout with increasing productivity does it for me.  All the marketing and management buzz words apply here; design complexity with shrinking time to market.

For layout designers in the custom and analog/mixed signal arena, who have increasing productivity demands, Virtuoso IC 6.1.3 and the Virtuoso Layout…

Formal verification can mean different things depending upon who you speak to. If I were blogging under Logic Design, it would probably indicate a series of loosely correlated opinions and observations on the topic of equivalency checking. However, this happens to be the Functional Verification forum and this blog about model-checking.

Model-checking: The process of checking whether a given structure is a model of a given…

You may recall a post I made a couple months ago about What's Good About Differential Pair Support in ASA?

In order to establish Differential Pair support for Design Entry HDL (DEHDL), the SPB16.01 release included enhancements to PCB Librarian which allow designers to define diff pair pins.

With the increased signal speeds of complex designs, differential pair signals are becoming more and more prevalent. In order to…