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Coming from the Cadence booth at Arm TechCon (camera Sean)

Academic Week

Monday: Andrew Kahng on The Last Scaling Levers

Tuesday: Rob Rutenbar is the Recipient of This Year's Kaufman Award

Wednesday: 10th Anniversary...

I think that Arm was successful in mobile (and subsequently in other markets) due to a couple of factors, mostly being in the right place at the time when two things happened, aka luck.

The first thing that happened was mobile phones took off, especially...

This week we return to the Internet of Things (IoT). My previous blogs on the subject – here and here – reviewed a presentation that Somshubhro Pal Choudhury, Partner of Bharat Innovation Ventures, gave at Cadence’s annual user conference, CDNLive...

As usual, Arm TechCon opened with a keynote by Mike Muller, Arm's CTO. His son is in mechanical design in some way and Mike told us he is applying for an internship. In a sign of the times, he is applying for an internship in Shenzhen. If you don't recognize...

Accelerating product time to market, achieving significantly higher productivity and efficiently working in global engineering teams are the key challenges being faced by designers. Team Design Authoring (TDA) feature of Allegro Design Entry HDL addresses these challenges by providing integrated team design environment. The design can be partitioned at a sheet or block level, and each designer can be assigned one or more…

In this week's Whiteboard Wednesdays video, the last of a three part series, Scott Jacobson ties together the technology implications of automotive electronics requirements and the effect they have on different memory model technologies.

www.youtube.com/watch

Paul Otellini was CEO of Intel from 2005-2013. He died in his sleep on October 2, aged 66. Apart from all the good things that happened on his watch, he is probably most famous for "missing mobile." In particular, when Apple and Jobs...

In the comments to blog #4, Frank Wiedmann asked about the correlation between the results of mismatch from Monte Carlo analysis and DC mismatch analysis. It is a fair question and here is a short blog to explore the topic. The example may not be realistic, but it is a useful for exploring the effects of mismatch on a circuit.  

Let’s start with a simple circuit—A resistively loaded differential amplifier with cascodes…

This morning Arm announced their Platform Security Architecture (PSA), a new way of protecting our ever expanding connected world. This is intended for all Arm-based devices from the lowest cost microcontrollers on up. There is a particular focus on...

Earlier this week, Jim Hogan hosted the next evening at San Jose State University on Preparing for the Cognitive Era, with Vishal Kapoor. If you work at or deal with Cadence, and his name seems familiar, that's because he worked at Cadence from 2003...

https://youtu.be/-9hc6xBOPFw

Coming from  SJSU Theater (camera Sean)

Monday: Arm Announcement (embargoed)

Tuesday: Cadence Announcement (embargoed)

Wednesday: Why Was Arm Successful in Mobile?

Thursday: Oski Formal Verification Club (with Arm and...

Recently, I wrote about Robert Lang's presentation on Computational Origami. He was a real paper master. The CTO of AMD is Mark Papermaster, although I think he is more of a silicon master than a paper master. At SEMI's strategic materials conference...

Rob Aitken is digging a bit deeper into what it would really take to connect a trillion things in his keynote at Arm TechCon How to Build and Connect a Trillion Things. What would those things be? What might unit volumes be? How could we power them...

In this week's Whiteboard Wednesdays, the second in a three-part series, Scott Jacobson discusses the drivers that are changing the requirements for automotive memory models.

www.youtube.com/watch

Diwali is finally here! One of India’s most favorite festivals, it is celebrated across the world not just by Hindus but by many faiths as the Festival of Light, a time to meet friends and family, buy new clothes, and indulge in rich and deliciously artery...

Sorry, you missed Oktoberfest (which is mostly in September anyway). But come to Munich in October for SystemC Evolution Day—a workshop on the evolution of SystemC standards held in Munich, Germany on October 18th. It’s a full day workshop, and the second iteration of a successful first run in May 2016. SystemC Evolution Day will feature several in-depth sessions about current and future standardization topics involving…

Chinese children are familiar with the opening lines of Romance of the Three Kingdoms:

The empire, long divided, must unite; long united, it must divide. Thus it has ever been.

As Ben Horowitz (of Andreesen-Horowitz) says in his new book, The Hard...

Like with any new product in market everyone is anxious about knowing all the features and then trying it out.  The display piece in the showroom and the purveyor are no less than an emancipator. Display piece helps us know how the product, test the areas...

Are we there yet? All verification suffers from the problem of trying to decide when enough verification has been done. It is not possible to exhaustively simulate everything on a chip and so completeness cannot be the criterion (exhaustion, however,...

In Part 3, we started to explore how to analyze the results of Monte Carlo analysis. In Part 4, we will consider the question, what is the relationship between process variation and the circuit’s performance variation? The tool for exploring the relationship process variation and circuit performance variation is mismatch analysis in the tool Virtuoso^® Variation Option (VVO). 

Let’s start by looking at a simple…

In Part 4 of the series, we looked at applying mismatch analysis as a design tool. In Part 5, we will continue to look at mismatch analysis by applying the technology  to other types of designs..

The first case we will look at is a circuit without a DC operating point. A dynamic comparator, see Figure 1, doesn’t have a quiescent operating point making it difficult to analyze.

In this case, the offset voltage is…

Today, Cadence announced that Teradyne has adopted the Xcelium™ Parallel Simulator for use in ASIC development. They’ve reached a 2x speedup with Xcelium when compared to their old simulation solution.

Xcelium has quickly become a key part of Teradyne’s verification environment, providing an easy-to-use, yet very powerful, tool that runs  fast and ensures high-quality designs. Beyond Xcelium, Teradyne…