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On October 20, 2016, 12 Masters and Ph.D. students mostly from Institute of Microelectronics, Tsinghua University visited the Cadence Beijing Office.

The group was welcomed by Tracy Zhu, Cadence Academic Network Program Manager in Asia Pacific. Then...

Enhanced Contour Routing is a new prototype feature in the Cadence® Allegro® PCB Designer 17.2-2016 that provides a more efficient method to add routing during Add Connect by following an existing connect line or a route keepin. This feature has been vastly improved over the legacy Contour feature by removing a continuous dialog popup, introducing a simple canvas-based two-state click use model, and enabling Sho…

The whole afternoon the second day of the Linley Processor Conference was dedicated to automotive. To show how important this has become, what used to be the Mobile Processor Conference is no more, and in 2017 there will be an Autonomous Processor Conference...

I wrote recently about the keynote from the Linley processor conference about network virtualization, and an analogy with server virtualization. One question that I know from when I worked at VaST and Virtutech is that the whole idea of virtualization...

https://youtu.be/wL43x-MOfWY

It's Automotive Week on Breakfast Bytes.

Monday: Mike Demler's overview of automotive and the NXP keynote from the Linley Processor Conference

Tuesday: Segars and Son, the opening keynote from ARM TechCon

Sophia Antipolis is in the south of France, a sort of research park carved out of scrubland on top of a plateau inland from Antibes (Antipolis is the Latin name for Antibes). It was created in the 1970s and built up slowly. The initial "companies" that...

We need our cars to be safe as the amount of electronics in them increases almost exponentially. One aspect of that is that the component suppliers need to provide Automotive Safety Integrity Level (ASIL) certification, which includes a formal assessment...

In this week's Whiteboard Wednesdays video, we discuss about integration of IP in a SoC context. Patrick Oury explains how to use Cadence Verification IP (VIP) to coordinate SoC activation together with functional tests coming from the external simulating world.

https://youtu.be/opRibfQUW-I

There are different conferences on microelectronics. There are the industry conferences, where the CEOs are telling how well their companies are prepared for or against the next disruption, these conferences have usually the best food. Then there are...

DVCon Europe took place last week for the third time. If you are in China, you have your own DVCon coming next year for the first time, April 19 in Shanghai. DVCon Silicon Valley will be February 27 to March 2. And there is a DVCon in India...dates to...

In the late 1970s, most scientific computing was done on digital equipment (DEC) Vax 11/780 computers. The operating system came with a couple of default accounts so that you could log in and configure things when you first got the machine. One was the...

This year's MemCon keynotes were given by Hugh Durdan, VP of the IP Group at Cadence, on Diverging Products for Diverging Needs: Where Will the Memory Industry Be in Five Years, and by Steve Pwalowski, VP of Advanced Computing Solutions at Micron...

On the second day of the Linley Processor conference, the keynote was by Bruce Davie. He did his PhD in computer science at University of Edinburgh (yeah, so did I) and worked for many years for Cisco before joining a company called Nicira, which got...

https://youtu.be/PHVpQ_-tmY8

Monday: The IoT attacks, with the biggest distributed denial of service attack ever

Tuesday: Highlights of DVCon Europe

Wednesday: Reliability and functional safety in automotive, from the TSMC OIP symposium

Thursday...

This year's Kaufman Award recipient is Andrzej Strojvas. He is the Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University (CMU) and is also the CTO of PDF Solutions. Last week, I went over to PDF in downtown San Jose to...

Web applications for electronics design provide an environment where users can apply their knowledge, and thus accelerate learning. These virtual laboratories provide plenty instruments and pre-built circuits or systems, that enable users to do experiments...

In this week's Whiteboard Wednesdays video, James David talks about the benefits of two types of error injection, predefined and callbacks.

https://youtu.be/BhTdY9fkF70

With cloud technology going vertical, everything is changing. The world is connected like never before—managing and processing large amount of data, every single second. Augmented/Virtual Reality is the latest game changer, even in its early stage of development and proliferation. The gathering of semiconductor experts at CDNLive Israel confirmed these and other trends are impacting everything from IP to tools to business…

Yesterday, I wrote about the new 12FDX process, which is a derivative of the original 28nm FD-SOI process developed by ST Microelectronics. Last year I talked to Thomas Skotnicki. He is the father of thin-box FD-SOI and its birth is an interesting story...

We are not talking about how your design compares to the next guys’, we’re talking about the PCB layer structure of your design, be it rigid, flex, rigid-flex, or using inlay technology. Stackup definition, more specifically accurate stackup definition, is critical for a wide variety of reasons. The arrangement of the various materials affect the computations and analysis for controlled impedance nets and…

The Story So Far

GLOBALFOUNDRIES had a 28nm Hi-K PolySi process. I think that even they would admit that they were late to market with it. They also announced that they were licensing 28nm FD-SOI from ST Microelectronics who developed it, and I think...

In this new age of complex designs and scaling of technology nodes, there are more number of wires per given square unit of area. As a result, applying constraints is considered wise to make sure signal integrity (SI) is taken care off well. It is due to this reason that circuit designers show a growing preference for using a larger number of constrained and managed nets. These constrained nets, if possible, can be used…

At the recent MIPI DevCon, Cadence's Ofir Michaeli gave two presentations on verification. The first was Effective Vertification of Stacked and Layered Protocols. Then he was back later in the day to cover Using MIPI Conformance Test Suites for Pre...