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When I think back back just a few years ago, there were only a handful of devices that noticeably responded to changes in their environment by sensing the presence of something or a change in position. Not that these were the only ones, but these were the ones that were part of my regular “consumer” interaction with the world in my daily life:

• Tilt sensors in game controllers then in tablets and smart…

In this week's Whiteboard Wednesday video, William Chen explains the many benefits of designing your SoC using a multi-protocol PHY.

https://youtu.be/_W4BRr1RL_Y

Cadence’s Tensilica team was honored with the Best Paper Award at the IP track at the Design Automation Conference last week for “Design in the Eye of the Hurricane—Building Optimal Vision Processing Systems.” The paper highlighted the technology behind the Tensilica IVP (Image/Vision Processing) DSP.

Cadence IP Group CTO Chris Rowen accepted the award (pictured) on behalf of the team which included…

1. Cadence Documentation Survey

Cadence is committed to providing high-quality documentation. To help us shape the future of Cadence documentation delivery, we welcome you to complete our survey.

2. Virtuoso Spectre Transient Noise Analysis

This document discusses the theoretical background of the Spectre solution’s transient noise analysis, its implementation and implications…

So you've looked at Google project ARA and you have the most brilliant idea for a module that would be the hardware answer to Angry Birds, you take the next step and download the Module Developers Kits (MDK), and then you realize that the platform is based on MIPI UniPro Switch. That's the first time your confidence is damaged as there is no other platform out there that is based on UniPro switch. When taking a deeper…

Many times a user would like to be able to modify the behavior of a program based on arguments on the command line. Let’s take as an example a user who would like to pass the name of a file which includes input parameters to the e program.

In the C language this can be done using argv, which is an array of strings where each array element represents a command line argument. However, since Specman and the simulator…

In the previous posts in this series on Multi-Language Verification Environment, we created a multi-language environment containing UVCs implemented in e and SystemVerilog. 

This environment is functional—exercising the DUT interfaces containing one system-level checker—but something is flawed in this picture. We have UVCs instantiated side by side, rather than in their “natural” location in the hierarchy. In a UVM…

Hi Everyone,

Last week I highlighted a video featuring Innovus User Interface Tips. Now that you know how to get around, what next? Innovus has a new, more streamlined design flow. Most designs should start with what's called the Standard Flow. There is a great document on support.cadence.com outlining this flow. I found it very interesting, and I can't wait to try it on my next design. You'll need an active support…

In the previous blog post, we demonstrated connecting a checker implemented in SystemVerilog to a monitor implemented in e.

In this post, we will show a fast way for adding a system-level data checker – using the UVM Scoreboard.  The UVM Scoreboard is an open-source framework, implemented in e, and is released as part of the UVM e Library. 

For adding a scoreboard to our XSerial-to-UBus environment, we define…

“The leading edge is 1 million gates.” That was the news when we approved IEEE Verilog 1364-1995 and the open VCD syntax standard for debug data interoperability. Now the leading edge is over 1 billion gates and it’s time to modernize VCD. If you stop by the Verification Academy booth at DAC on Tuesday June 9 at 5pm, you’ll learn how.

Now that I’ve piqued your interest, lets take a look at why…

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the basics of Tensilica configurable processors and what is involved in using them.

https://youtu.be/5rnQyoTLVvY

Hi Everyone,

No doubt by now you have heard about the Innovus Implementation System, our next-generation physical implementation solution. It's always a bit scary to move to a new tool, but let me assure you that if you are a current Encounter user, you will be able to get around just fine in the Innovus system. A lot of the user interface will look very familiar to you, but there are some important changes and improvements…

I attend IEEE 802.3 Ethernet standards meetings and blog about them from time to time. (For past blog posts, see the list at the bottom of this post).

The most recent 802.3 meeting was held in Pittsburgh and has just finished. Pittsburgh is very interesting with fine buildings and nice parks. It sits at the confluence of two wide rivers and was a major transportation and steel town in its day. I've included some photographs…

In the previous blog post, we created a simple multi-language verification environment, running UVCs implemented in SystemVerilog and in e.

The architecture of the environment is as pictured here:

We will now add to this environment a system-level checker, implemented in SystemVerilog.

A standard recommended way for passing items is via TLM ports. For connecting ports instantiated within components implemented in…

Seems that by now, every one in the industry realizes that multi-language verification environments are not a faraway vision, something only for eccentric verification experts. Multi-language is here, simply because we need it.

Because there is no sense in throwing away a high-quality verification environment just because someone else prefers coding in a different language. Because there is no sense in forcing engineers…

This blog starts with a description of a debugging session of a mysterious behavior we encountered. Unlike a good mystery book, I will tell you upfront who did it—deep_copy(). In the second part of the blog, we’ll recap e’s copying methods, and we’ll understand how to avoid such mischief.

The mystery started when we saw that, in one verification environment, a struct that was expected to perform…

With the USB protocol being so popular nowadays (and frankly speaking, was there ever a time it wasn’t?), there are many advantages of enabling USB in an application, like versatility, ease of use, proliferation within the industry. However, there are also some hidden potential traps, which I'll discuss in more detail here.

USB design IP has…

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty continues his discussion on DDR4, with a focus here on bank grouping of DDR4.

https://youtu.be/_4lWfP5eDcQ

Most of our customers use the product documentation, Help, and Cadence Online Support capabilities while using our products and flows. There is a team working on developing the next generation of Cadence documentation and the Help utility.

The Cadence Online Support - Cadence Support News area recently posted the following:
“Cadence is committed to providing high-quality documentation. To help us shape the future of Cadence…

Think that DAC is all about EDA tools? Not anymore. This year there are over 100 presentations in the IP track, plus other sessions that are all about IP. After all, it’s almost impossible to find a chip design these days that doesn’t employ some type of IP.

Come see many of us from the IP Group at Cadence at DAC, June 7 – 11, at Moscone Center in San Francisco. You can’t miss the Cadence booth—we’re…

I’ll never forget covering a presentation that then-National Semiconductor CEO Brian Halla gave about a dozen years ago.

He talked of a time when electronics would be everywhere, taking in the analog world and converting that intake into useful data. In those post-911 days, he envisioned remote and even flying security cameras around structures like the Golden Gate Bridge. It was before drones took off and before…

1. Spectre PSPICE Netlist Support

Spectre technology enables the user to include PCB components in PSPICE format into a Spectre integrated circuit simulation. The solution is based on the approach of using a regular Spectre simulation including the Spectre simulator control statements, but additionally allowing inclusion of user-defined sub-circuits in PSPICE format.

2. Setting Up Liberate MX for…

In this week's Whiteboard Wednesdays video, Jacek Duda explains the implications that the Type C Connector has on the USB On-the-Go Controller.

In the 16.6 Allegro PCB Editor release, net associations to split planes are now stored in the database. This reduces chance of error when re-generating split planes on positive or negative layers. The former use model required re-assignment of a net during the command, which was error prone and cumbersome.

When a split plane is regenerated, the net choice dialog for each shape is set to the default net that will be assigned…