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In this week's Whiteboard Wednesdays video, the first of a two-part series, Charles Qi highlights the new MIPI audio interface standard, Soundwire. Charles details how Soundwire supports new audio applications and can connect to multiple audio interface devices.http://youtu.be/LKDjhraDves

Read on for more details …

Customized Tooltips

You can now utilize TCL that can override the Tooltip being displayed.

Try this example:

1. Enter the following TCL commands in the Capture TCL Command window -

proc CustomToolTipForPageObjectsEnabler {args} {

return true;

}

proc GetCustomToolTipForPageObjects…

This article highlights the use of list pseudo-methods constraining the content of lists, which is relatively new and offers a lot of power in terms of modelling, performance, and debugging.

Ethernet-based communication is getting more pronounced today and will continue to do so in the future. This increases the need to be able to verify devices that are capable to handle specific bandwidth requirements. Shaping constrained…

Given that CES is a novelty-focused event, it is crucial that innovative companies such as Cadence use this opportunity to demonstrate the technology behind the latest consumer gadgets. This year, however, we’re taking everything a step further. During CES 2015, not only will we present our individual products but also complete systems solutions that integrate Cadence^® Tensilica^® IP (TIP) with Design IP …

Right form the start Specman has been very good at generating constrained random stimulus. Value generation guided by constraints is achieved with an algorithm within Specman that is at the very core of the tool. And solving constraints is one of the most outstanding features of Specman itself.

In the early days of Specman, the constraint solver (called PGen) had been continuously augmented and improved over time. However…

In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog solution for SoC Interconnect Verification. Two products are provided: the Interconnect Validator, which monitors fabric behavior, and the Interconnect Workbench for performance analysis. The combined solution delivers functional verification along with latency and bandwidth analysis to fine-tune interconnect performance. 

http://youtu…

An updated version of the UMV-ML Open Architecture library is now available on the Accellera uploads page (you need to login in order to download any of the contributions).

The main updates of version 1.4 are:

• UVM-SV library upgrade: This release includes UVM-1.1d, enabled for work in context of UVM-ML, replacing the previous UVM-1.1c version
• Portable UVM-SC adapter added: Enabling usage of UVM-ML with vendor-specific…

Key Findings:  There are a host of issues that arise in mixed-signal verification.  As discussed in earlier blogs, the industry trends indicate that teams need to prepare themselves for a more mixed world.  The good news is that these top five pitfalls are all avoidable.

It’s always interesting to study the human condition.  Watching the world through the lens of mixed-signal verification brings an interesting microcosm…

In this week's Whiteboard Wednesdays video, Bob Salem discusses the advantages of embedding a LTE and Advanced LTE analog block on the SoC to support many of the mobile applications in the market today.

http://youtu.be/SGgfOr8gtfw

The ‘dual_sided_component’ property in the Allegro PCB Editor 16.6 release can be leveraged to support vertical component applications. Apply the property ‘dual_sided_component’ to the symbol definition. Assuming a two-pin component, you will map pin 1 and pin 2 to unique padstacks, each with a ‘Begin’ or ‘End’ layer pad defined. The base layer is established using the Embedded Layer Setup form. The alternate…

Two great documents, aiming to make life easier for a verification engineer, were published in the past year. Written by Cadence support specialists with years of experience in problem solving, these documents go over all the aspects in the Specman-Simulator Interfaces domain, present what kind of problems the engineer might get, how to identify them, and how to analyze the problems all the way to possible solutions.

Over the years I've often hoped to have the ability to show someone (a customer, or one of our field engineers) a bit of e code, and explain what it actually does. People say that a picture speaks more than a 1,000 words, so you could say a bit of code does have the same effect on engineers.

Well, since the beginning of this week you can do exactly that with your e code on a very neat website called http://www.edaplayground…

In my previous blog post, I wrote how much better than the existing Type-A and Type-B plugs the recently announced Type-C connector will be. Actually, the Type-C connector is only a part of the equation of how better the USB ecosystem will become when all USB specifications announced this year find their places in future devices. The others are USB 3.1, with its up to 10Gbps data rate, Power Delivery 2.0, and Alternate…

Key Findings: Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it.

As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the digital…

In this week's Whiteboard Wednesdays video, Lou Ternullo explains the DRAM trends in today's consumer market. He deep dives into the comparison between LPDDR4 and DDR4 DRAM.

http://youtu.be/pxuixROtlPI

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty reviews evaluation criteria when purchasing a DDR PHY IP solution. Kishore details topics such as power, performance, and area (PPA), interoperability, DFI, and floorplan flexibilty.

www.youtube.com/watch

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase.

Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation of a mixed-signal SoC using Palladium XP”. Advantest makes advanced electronics test…

The 16.6 Allegro PCB Editor release contains two new selection options, lasso and path, which are available with commands that normally support temp groups; ‘Move’ and ‘Highlight’ are two examples of those commands.  If working in an application mode, you can access these selection options from the RMB – Selection Set menu:
       
                

Read on for more details …

Let’s look at a few examples that…

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification IP (VIP) and how it allows engineers to know they have a thoroughly tested design that complies with the interface specification.

http://youtu.be/NZyFL4TbeME

Recently, an article was published in Printed Circuit Design and Fab about Multi-Fabric Planning for Efficient PCB Design (see page 22 of printed magazine).

Today's BGA-style packages have a significant impact on PCB layer count, route complexity, and cost. Efficient BGA net assignment and patterning of power and ground pins can make the difference between a four- and a six-layer PCB. Historically, there's been minimal…

There has been a flurry of activity on COS over that past couple of months. I can't even come close to listing everything, but here are some of the highlights. Be sure to check out the "Training Bytes" section at the end of this post for information on a recent initiative in which Cadence training experts are publishing short video excerpts from our most popular classes.

0. Many of the product…

I attended the Gartner Semiconductor briefing on Oct. 23, 2014, the theme of which was “The Internet of Things: Use Cases that Move Beyond the Hype.” Most attendees were from the semiconductor industry, of course.

Huge numbers like the following were thrown out:

• In 2020, 8+ billion things shipped in one year.
• This will generate 35 billion semiconductor devices requiring 6 million wafers in 2020.

One…