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In this week's Whiteboard Wednesdays, Kishore Kasamsetty discusses the low-power advantage that LPDDR4 provides over the LPDDR1/2/3 in the mobile market.

www.youtube.com/watch

The Add Connect with Offset command in Allegro PCB Editor 16.6 is designed to primarily address the requirement to route with non-standard angles to help minimize impedance discontinuities while routing across fiberglass substrates. Other routing applications may be applicable as a result of this implementation, including, but not limited to, package/connector breakout or routing associated with tester cards.  

The Offset…

Plenty to keep you busy this month.  Lots of RAKs, videos, and new Quick Start Guides and FAQs.

Application Notes

1. Using Annotation Browser with Virtuoso IPVS

Learn how to invoke the Annotation Browser and have it always appear docked to a specific location of the layout window, how to customize the Annotation Browser, and how to automatically set the visibility of the error markers.

2. AMS Designer INCISIVE Command…

This year, the Design Automation Conference (June 1-5 in San Francisco) has put a lot of effort into great content for IP buyers, and Cadence has great plans to highlight our IP. Here are some of the things you can see at DAC this year:

Booth 2610 demo 

See Cadence's large library of IP and verification IP for memories, interfaces, analog, and peripherals. Join us for a fun-filled game and test your knowledge of the protocols…

Last year, I wrote a blog post entitled Modeling Oscillators with Arbitrary Phase Noise Profiles.  We now have an easier way to do this.  

Starting in MMSIM 13.1, you can specify the phase noise as an instance parameter in Spectre sources, including port...

In this week's Whiteboard Wednesdays, the second installment of a three-party series, Kevin Yee continues his earlier discussion on "taking command" of MIPI PHYs. Here, Kevin discusses M-PHY, its architecture, and the protocol's functionality in mobile devices.

www.youtube.com/watch

The Allegro PCB Editor 16.6 ‘Show Measure’ command now displays results in database and alternate units.  Alternate unit display requires the enablement of the user preference variable ‘showmeasure_altunits’. ‘Show Measure’ also supports a measurement between padstacks even if a common layer does not exist. This will be helpful when measuring mask-related geometry to conductor.

Read on…

Why high yield analysis?

In this week's Whiteboard Wednesdays, Kishore Kasamsetty provides a history on DDR4 technology. He also walks you through the improvements of DDR4 over DDR3, as well as the memory standard's specifications and the challenges of meeting these specifications.


www.youtube.com/watch

Embedded Vision Summit West 2014 on May 29 at the Santa Clara Convention Center provides a unique opportunity for engineers to learn about the hottest technology in the electronics industry: embedded computer vision, which enables "machines that see and understand."

Summit highlights include:

• Keynote talks by industry luminaries from Facebook and Google
• Two technical conference tracks featuring "how-to" presen…

In this week's Whiteboard Wednesdays, Tom Hackett takes a closer look at simulation verification IP (VIP), and how these IP cores help verify designs with protocol checks, test sequences, and other capabilities.


www.youtube.com/watch

For years we've watched the e and SystemVerilog race via countless presentations, articles, and blogs. Each language is applied to SoC verification yet the differences are well documented so any comparison is subject to recoding from one language to the other. This makes a direct performance comparison difficult to measure. Until now.  

On April 21, 2014, SystemVerilog and e toed the line for the first direct SoC race…

The vast majority of SoCs today are advanced mixed-signal designs. The old mixed-signal world looked like an analog environment on the left bolted to a digital environment on the right. Depending on which engineering group was responsible for final assembly, one part would be treated as a black box and the two parts would be bolted together at the system-on-chip (SoC) level. But today's mixed-signal designs have multiple…

In this week's Whiteboard Wednesdays installment, Priyank Shukla highlights wireless transceivers and protocol standards 802.11x and LTE/LTE-A. Wireless transceiver implementation options consisting of RF, Analog Front-End (AFE), and Digital components are examined.


www.youtube.com/watch

In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3.  Here are more new features that are now available in Virtuoso ADE XL in the recently released ISR6.

• Notes can be added to tests, variables, corners, parameters, and histories. This allows you to document information about important items in your setup…

Hi All,

Here's another great new feature that I've found very helpful...

Broadband SPICE is a new tool for S-parameter simulation in Spectre RF.

In the MMSIM13.1.1 (MMSIM13.1 USR1) release (now available on http://downloads.cadence.com), a...

Hi Folks,

A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job?  I use distributed processing and need to provide an estimate before submitting jobs."

The...

In this week's Whiteboard Wednesdays installment, Kevin Yee discusses what it means to "take command of MIPI PHYs". This is a first of a three-part series on the topic. Here, Kevin will introduce you to D-PHY and its architecture, and how the protocol meets the requirements of mobile devices.

www.youtube.com/watch