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System, PCB, & Package Design : Make Your IC Packaging Documentation Labels Smarter with 16.6 SiP and APD

Jeff Gallagher

Documentation is key when completing any IC package substrate design. Without it, any number of problems can arise - from incorrect bond mapping between die pads and bond fingers to die being stacked in the wrong order. Ensuring that your documentati...
- 17 Jan 2013
Verification: 2013 CES: Top 4 Trends Benefiting EDA

jvh3

While a variety of EDA customer segments are growing, consumer electronics continues to drive the lion's share EDA of industry revenues. Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business. While I couldn't personally attend CES this year, like last year my two trusted agents (specifically, Unified Communications …
- 17 Jan 2013
System, PCB, & Package Design : What's Good About Viewing Constraint Differences? See for Yourself in Allegro 16.6!

Jerry GenPart

Starting with the Allegro PCB Editor 16.6 release, we can compare two constraint databases and view the constraint differences. This provides an efficient opportunity for designers to determine the differences between 2 designs.

Read on for more details
Generate a Constraint Difference Report
1. Open the Constraint Manager.
2. Select File > Import > Constraints.
3. The 'Import Constraints' dialog box is displayed. Select…
- 16 Jan 2013
Digital Design: Five-Minute Tutorial: Creating An EM Model File

Kari

One of the least-fun parts of running power and rail analysis has always been coming up with the electromigration (EM) model file. In the past, this involved cracking open the process design rule manual, finding the appropriate equations, and creating a spreadsheet to calculate all the numbers needed for the various metal width and via sizes. Then, this information had to be put in the format of the model file used by…
- 14 Jan 2013
Analog/Custom Design: Virtuosity: 10 Things I Learned in December By Browsing Cadence Online Support

stacyw

In addition to the R&D engineers who actually develop our software, the folks in many other groups here at Cadence put a lot of time and effort into creating a wide variety of documents, presentation and videos to help our users learn to use the software more effectively. Today we're kicking off a new monthly series to highlight interesting and useful content recently added to the Cadence Online Support website in…
- 14 Jan 2013
Analog/Custom Design: Library "Safe Margins" -- Are They Really Saving Your Design?

AElzeftawi

Designers need to radically re-think their strategies for timing closure to get the most out of process technologies that are becoming readily available. The additional burdens of creating electrical cell views for timing, power and signal integrity, accounting for process variability, managing leakage power, and hitting a low power budget make obtaining market leading performance extremely difficult.
To overcome these…
- 10 Jan 2013
Analog/Custom Design: SKILL for the Skilled: Part 6, Many Ways to Sum a List

Team SKILL
In a previous post I presented sumlist_2b as a function that would sum lists of length 0, 1, or more.
(defun sumlist_2b (numbers) (apply plus 0 0 numbers))
Unfortunately sumlist_2b cannot handle extremely long lists. In this posting, I will introduce sumlist_6 which does not suffer from this limitation.
This posting will not introduce any new SKILL++ primitives. Instead, it will use several primitives which have been…
- 10 Jan 2013
System, PCB, & Package Design : Customer Support Recommended – Pin Swapping in Allegro Design Entry CIS and PCB Editor

Naveen

Placement and routing have always been an integral part of printed circuit board design. The productivity of the product is often (if not always) achieved best if the PCB has a proper placement of the components and effective routing to support the placement. With the increased complexity of the designs and smaller board sizes, routing of signals has become more challenging. Designers are always looking for ways to ease…
- 9 Jan 2013
Analog/Custom Design: Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitment

Sathish Bala

Cadence holds a leading position in the EDA industry due to its broad product portfolio catering to digital and analog designs and the ever popular mixed-signal designs. With its immense technical and market leadership based on the Virtuoso platform for analog design and Encounter platform for digital design, Cadence EDA products helps designers achieve productivity gains and predictable design closure for today's complex…
- 8 Jan 2013
Verification: Specman: Determining a Good Value for optimal_process_size

teamspecman

Specman's Automatic GC Settings mechanism is aimed at eliminating the need for users to control the parameters which determine each Garbage Collection's behavior.
Setting config mem -automatic_gc_settings=STANDARD tells Specman to calculate all the parameters, to ensure that Specman's memory management system works in an optimal way.
The only parameter that is left for the user to play with is the -optimal…
- 1 Jan 2013
Verification: System Design 2012 – Real Users Achieving Real Results!

fschirrmeister

This morning the final success story my team has been working on for this year went live. Texas Instruments reports on how they achieved greater than 90% accurate correlation between an architectural power estimation and actual silicon! This des...
- 21 Dec 2012
RF Engineering: Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 2

Tawna

Greetings,

Simulating crystal oscillators got a lot easier in MMSIM12.1...We have made enhancements to both Harmonic Balance and transient analyses.

In Part 1, I discussed Improvements to the Harmonic Balance use model. With the new streamlined Choosing...
- 20 Dec 2012
System, PCB, & Package Design : Be Among the First IC Packagers to Experience the New GDS-II Stream Interface in 16.6

Jeff Gallagher

For most IC package designers, the GDSII format is a part of daily life. You may receive stream data from your IC designers or partners which you must convert into die components for placement on a package substrate, or perhaps you export stream data...
- 20 Dec 2012
RF Engineering: Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 1

Tawna

Greetings!

Simulating Crystal Oscillators got a lot easier in MMSIM12.1...We have made enhancments to both Harmonic Balance and Transient analyses.

In Part 1, I’ll cover Improvements to the Harmonic Balance use model. With a streamlined Choosing...
- 19 Dec 2012
Verification: University of Aizu and Cadence Collaborate to Deliver a Course Featuring High-Level Synthesis

Jack Erickson

Today we issued a Japan-only press release announcing a high-level synthesis joint development program with the University of Aizu. This is Japan's first university-level course teaching high-level synthesis for semiconductor design. Here is the ...
- 17 Dec 2012
Verification: C-to-Silicon 12.2 Available for Your Holiday Shopping List

Jack Erickson

The winter holiday season is that special time of year when we get bombarded with catalogs, emails, television commercials, banner ads, store displays, and any other method to get our attention on something that somebody is trying to sell. Having bee...
- 13 Dec 2012
Analog/Custom Design: Mixed Signal Technology Summit Proceedings Now Available

nizic

In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees used the opportunity to ask questions, share experiences and network.
Dr. Chi-Ping Hsu, Cadence Senior Vice president…
- 13 Dec 2012
Verification: Securing the Internet of Things

fschirrmeister

While I had looked at the challenges of hardware/software integration in various application domains like automotive, industrial and wireless before, I had the most unsettling experience last week at the Amphion Forum in San Francisco in the app...
- 12 Dec 2012
System, PCB, & Package Design : What's Good About RF PCB and Layout? 16.6 Has Many New Enhancements!

Jerry GenPart
The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over the next several weeks. Here are some major layout related enhancements:
Snap Enhancements
Add Connect Enhancements
Modify Connectivity Enhancements
Add Component Enhancements
Scaled Copy Enhancements
Single Segment Connection
Route with Any Angle Bend
Read on for more details …

Snap Enhancements

In Allegro 16.5, when you snap an…
- 11 Dec 2012
Verification: Avoid Overly Long Expressions in Specman e Code

teamspecman

When you write your e code, a good practice is to avoid expressions that are "overly long" even though they are completely legal. While there is no hard definition of what constitutes an overly long expression, such long expressions can lead to human errors and parser processing errors.
Very long expressions are hard to read and understand. This also makes them error prone, as an accidental syntax error in the…
- 11 Dec 2012
Digital Design: SPICE Correlation Made Easy by Encounter Timing System (ETS)

MJ Cad

Hello, and welcome to my first blog!
As an application engineer in customer support, I have received quite a few queries on how to do SPICE correlation of timing numbers. This blog is intended to help users understand the flow/methodology for doing SPICE correlation of static timing analysis (STA) timing results using Encounter Timing System (ETS).
As we know, users do correlation of the critical paths in timing analysis…
- 10 Dec 2012
Verification: Update to the Linux Kernel Message System

jasona

A few months ago I wrote an Introduction to the Linux Kernel Message System. As with all software, especially Linux, things get out of date and need updating. The Linux 3.5 kernel contained changes to the kernel message system that are relevant to my...
- 7 Dec 2012
System, PCB, & Package Design : Leverage System Planning to Maximize Performance of Silicon Interposer

TeamAllegro

Recently, an article was published in Chip Scale Review by Cadence product manager Kevin Rinebold talking about maximizing the value of silicon interposer technology using system planning (see page 30). Today’s semiconductor technologies ...
- 6 Dec 2012
System, PCB, & Package Design : What's Good About RF SiP and Data Management? Look to 16.6 and See!

Jerry GenPart

The 16.6 Allegro RF SiP product has 3 major enhancements to improve your productivity.

Read on for more details …

Data Management of Virtuoso SiP Views

In release 16.6, Virtuoso SiP Architect is enhanced to support data management of SiP views through the Virtuoso Library Manager.
To enable this, files generated in the Virtuoso-SiP Layout flow are now generated in the lib:cell:view format. Starting in the 16.6 release…
- 4 Dec 2012
System, PCB, & Package Design : Minimize Your Mouse Clicks in IC Packaging with New Customizable Wire Bond Application Mode in 16.6

Jeff Gallagher

Whether it is reducing mouse clicks, minimizing access to menus, eliminating the need to modify the find filter, or providing direct access to change options panel settings without leaving the canvas, anything that can be done to improve the efficien...
- 4 Dec 2012

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