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As outlined in a prior post, new advances in formal and multi-engine technology (like Incisive Enterprise Verifier  or "IEV") enables users to do complete verification of design IP using only assertions (i.e. no testbench required!) -- especially for blocks of around 1 million flops or less.  Given this premise, it's natural to ask: "OK, but how does formal and multi-engine assertion-based verification…

Since the initial release of Advanced Constraints, one of limitations was that formulas had to be recalculated manually. This recalculation could be done on an individual basis or for the entire design with the Calculate All command. The Online Formula Calculation feature addresses these limitations by tracking the dependencies that formulas have on design objects and updating the formula automatically.

The SPB16.3 release…

If you were not able to attend this recent live webinar, or were able to and would like to share the content of this webinar with colleagues, you can find an on-demand recording by clicking and registering here:

Managing parasitics in the back end

In this third of a three part webinar series on parasitic aware design, Jeremiah Cessna and Sravasti Nair present an overview and demonstration of a back end analog IC design…

Feedthrough insertion is a subtly crucial task that naturally arises in hierarchical digital design.  There are several types of approaches we can use to allow signals to traverse across a chip, but the most common and effective I've seen is where buffers are inserted in neighboring partitions.  This eliminates top-level routing and more importantly takes the top-level timing closure task and makes it part of block…

The SPB16.3 release of Allegro PCB Router is now aligned with Allegro PCB Editor's approach for verifying mechanical hole objects.

Antipad as Route Keepout (or ARKs)

The Antipad as Route keepout option can be enabled in pad_designer:

 

The ARK on option is translated to a SPECCTRA dsn file as shown in example below:

  (padstack PAD125
   (plating nonplated)
   (ark on)
   (type thrupad)

The new behavior of Allegro PCB Router with…

If you were not able to attend this recent live webinar, or were able to and would like to share the content of this webinar with colleagues, you can find an on-demand recording by clicking and registering here:

Managing parasitics in front end

In this second of a three part webinar series on parasitic aware design, Nigel Bleasdale and Stacy Whiteman present an overview and demonstration of a front end analog IC design…

As 2010 ends and 2011 begins, the most important thing that came out of the Universal Verification Methodology (UVM) was the UVM Reference Flow.  We are thrilled with the results coming from this community contribution. With over 1,000 downloads already, it is clear that UVM has moved into the mainstream -- not a bad year at all.  Not only will the UVM libraries officially be released from Accellera after a significant amount…

If you were not able to attend this recent live webinar, or were able to and would like to share the content of this webinar with colleagues, you can find an on-demand recording by clicking and registering here:

Parasitic Aware Design - A Complete Analog Design Flow

In this first of a three part webinar series on parasitic aware design, John Stabenow presents a high level overview of an end-to-end analog IC design flow…

The acid test of any conference is how long after the keynotes, panels, and demos wrap up, the information and lessons learned linger in your mind.  Like this fall's CDNLive series, ARM Techcon 2010 is passing the test of time given the raft of serious new technology announcements (the significantly enhanced Mali-T604 Graphics Processor technology (GPU) is but one example) in addition to the meaty content presented…

In my last blog post, I related a story from my engineering past in which I learned the hard way about the value of anticipating and verifying corner-case conditions. That story was technical in nature, having to do with inadequate verification of software. However, sometimes the corner cases we encounter in life are not technical, but rather a series of relatively inconsequential incidents that line up in just the right…

The SPB16.3 release of Allegro PCB Editor now provides the ability to resize line width and gap of differential pairs. Designers are faced with challenges driven by time, cost and quality. A change request can come from the electrical engineers that mandates that differential pair gaps and widths be resized. This can entail hours to hundreds of hours ripping up and rerouting entire sections of the design to the new constraints…

OK, so the title is perhaps a little optimistic but I'm playing off the saying "keep your friends close, but your enemies closer" (The Godfather Part II: Francis Ford Coppola and Mario Puza). The corollary in custom design is to bring the understanding of parasitic effects as early as possible in the design flow, so there is less chance of surprises later.

In custom design there are a few ways…

Heads-up Team Verify subscribers: on his "Industry Insights" blog Richard Goering just interviewed Zocalo president Howard Martin about assertion-based verification methodology -- including the dangers of an ad-hoc approach to ABV.  To read the interview, click here.

For some additional background on Zocalo, recall this discussion from DAC:

If video fails to open, click here.

Additionally, Zocalo has been…

The SPB16.3 release of OrCAD Capture now allows you to create intersheet references on flat designs, simple designs, and complex hierarchical designs. Design navigation in Capture now also includes a signal navigation feature to navigate through the connected signals on a design. This feature allows you to select a signal that you want to trace and then browse through all the connected signals on the design.

Intersheet…

There were several questions about measuring transistor f_max in comments posted to my previous Measuring Transistor f_t and Simulating MOS Transistor f_t blog posts. So in this posting we will look at simulating transistor s-parameters and device characteristics...

An obvious criticism of my previous post SKILL for the Skilled: Making Programs Clear and Concise is that clarity is subjective. What is clear to one person may be confusing to someone else, especially to someone who is accustomed to doing things the hard way.

I'd also suggest the converse is also true. If you are accustomed to using a programming language that encourages an imperative style, you may become…

Preface: are you having trouble (re-)igniting interest in formal, muti-engine, and Assertion-Based Verification (ABV) among your colleagues and management?  If so, the following article is the perfect primer to share with such skeptics (whose knowledge of ABV might be way out of date.)

Like many things in EDA, what I'm about to say isn't conceptually new, but after years of development and promises the technology and methodology…

Mechanical part support! It's here in the Allegro Design Workbench (ADW16.3) release! 

There are new data model types in ADW16.3 that provide a solution for the support of mechanical models in the library and design flow. The mechanical model types supported in this release include three basic model categories – Allegro PCB Editor, Design Entry HDL (DEHDL), and Mechanical Kits.

Allegro PCB Editor mechanical models…