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Hi All,

Here's another great new feature that I've found very helpful...

Broadband SPICE is a new tool for S-parameter simulation in Spectre RF.

In the MMSIM13.1.1 (MMSIM13.1 USR1) release (now available on http://downloads.cadence.com), a...

Hi Folks,

A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job?  I use distributed processing and need to provide an estimate before submitting jobs."

The...

In this week's Whiteboard Wednesdays installment, Kevin Yee discusses what it means to "take command of MIPI PHYs". This is a first of a three-part series on the topic. Here, Kevin will introduce you to D-PHY and its architecture, and how the protocol meets the requirements of mobile devices.

www.youtube.com/watch

Anyone who has ever played a musical instrument knows how hard it can be to keep the instrument in tune when subjected to variations in weather conditions. Heck, in 2009, Yo-Yo Ma and friends (sorry, he gets top billing because I used to play the cello) pantomimed their performance at the Presidential Inauguration because their instruments wouldn't function properly in the frigid temperatures. Guess they didn't want to…

Highlights for this month include lots of useful Physical Verification System (PVS) appnotes and several blog articles on advanced analyses and flows in Analog Design Environment (ADE) GXL.

Application Notes

1. Physical Verification Checks and Generic Tips

Concise overview explaining the basics of the various DRC and LVS checks in rules files.

2. Recommendations and Tips for the PVS DRC Flow

Includes sections on…

The 16.6 release of OrCAD Capture has a couple new productivity enhancements centered around how reference designators are assigned to components in the schematic.

Read on for more details …

Design Level Auto-Reference Designator Assignments
In 16.6, in addition to the schematic level annotation of reference designators, you can also perform a design level annotation by selecting the Design Level option:

The previous…

Development Model for ADE and ViVA

Virtuoso Analog Design Environment (ADE) and ViVA follow a development model that allows new content to be added in every third ISR.  These content ISRs receive additional usability testing, product validation, and demonstrations and beta testing with customers. This development model gives R&D long enough development cycles to add meaningful content while ensuring that quality and stability…

In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application called Hosted Virtual Desktop, which supports increasingly mobile workers who want to use any smart, connected device to access corporate data resources.  Charles goes into detail about how Cadence IP can help expand the application to help businesses make mobile workforces more efficient.

www.youtube.com/watch

In my first blog of this quarterly series, I focused on how Rapid Adoption Kits (RAKs), developed by Cadence engineers, are enabling our users to be productive and proficient with Cadence products and technologies.  

In this second quarterly blog, let me explain the "Once Resolved, Reused Forever" internal process for documenting knowledge on https://support.cadence.com/. It ensures that we are not solving a problem…

Friends, you would probably agree that sharing knowledge is a practical way to solve business problems, and contributes to business goals. Thought I'd share some great content that I came across while navigating through https://support.cadence.com/

Rapid Adoption Kits:

Static Timing Analysis using Tempus (Signoff Timing Analysis) 13.2

With the help of this RAK (rapid adoption kit) you will learn how to perform static…

Over the past couple of years there has been some interest in applying a software development technique called unit testing in the hardware development flow. One of the reasons is that unit tests allow customers to validate their testbench in isolation, enabling very fast and thorough tests. Some customers have developed their own framework to accomplish this testing. In the Incisive 13.2 release, Cadence has introduced…

In this week's Whiteboard Wednesdays, Scott Jacobson completes his three-part series on the Memory Wall with a discussion on the different 3D memory solutions today and their market applications. You may recall that in the first segment, Scott examined how CPU performance outstrips memory transfers, and discussed options available to system designers, such as 2D solutions. In the second part of this series, Scott, took…

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. You can also compare the relative importance of the contributing instances.  The analysis results can aid in making…

www.youtube.com/watch

In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of new and updated mobile interfaces for mobile SoCs. These interfaces are broken down into three catagories—SoC fabric, memory, and chip-to-chip—and include ARM AMBA 4, ARM AMBA 5, OCP, DDR, LPDDR, LPDDR3, LPDDR4, Wide I/O, Wide I/O2, DRAM, eMMC, eMMC5, UFS, CSI-3, SoundWire, USB, PCIe, and SSIC.

www.youtube.com/watch

While there are several videos available for Allegro Design Entry HDL (DEHDL) in Cadence Online Support as well as in the product installation documentation folder ($CDSROOT/doc), there are times when a new specific video is produced for product features. Of course, there are many videos available for all the SPB products. Recently, several new videos have been produced for some of the more common functionality areas…

Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes.  However, redesign of circuitry is time-consuming, so it is common to migrate existing designs from previous projects, often from one process node to another.  Additionally, migration is also required for:

• Second sourcing on a similar process from a different foundry
• Reusing IP in next…

1. Only a single designer can work on the physical view of the design at one time
2. Multiple physical designers can work…

In this week's Whiteboard Wednesdays episode, Tom Hackett discusses why over 500 customers consider Cadence Verification IP to be the S.M.A.R.T. choice when looking to verify their SoC designs.

www.youtube.com/watch

In this week's Whiteboard Wednesdays installment, Cadence's Moshik Ruben takes a deeper look at the MIPI protocols that are the leading choice for certain mobile interfaces. Even though MIPI protocols are a top choice, however, they are being challenged by mobile versions of PCI Express and USB. Given this landscape, what does the future look like for MIPI and its challengers?  Watch this short video to find out…