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At the upcoming DVCon (in San Jose, CA February 25-28), Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here).  However, Team Verify would like to alert users of Cadence Incisive formal and multi-engine tools, apps, and assertion-based verification (ABV) to the following papers and posters focused on this domain.

* Session 2, Tuesday Feb. 26, 9-10…

At the upcoming DVCon (in San Jose, CA February 25-28), Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here).  Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and e language-related content, or be of general relevance to Specmaniacs.  Hence, if you are going to the conference, please consider…

Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos.

Take the time to browse through these videos.  Everyone will benefit, even if you are a new user looking for a debug solution…

The Allegro FPGA System Planner (FSP) 16.6 release offers major improvements in Auto-interactive pin swap (“Planning Mode”) with the addition of “Auto pinswap” functionality. Using three different algorithms – Reassign Bundle Pins, Rake Order, and Breakout Order – you can re-optimize entire bundles (the existing 16.5 manual pin swapping functionality has been retained). The communication between …

What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology.

Problems of Advanced Node Design

When designing with the most advanced node technologies including 22nm technology and beyond, you will encounter many new problems that no…

Components in a design communicate with each other based on some rules or protocols. These protocols contain a group of signals with some relationships defined between them -- for example byte lanes, clock and strobes. The Allegro Design Entry HDL 16.6 release enables the use of these protocols or signal grouping by introducing support for hierarchical interface definitions.

These definitions can be entered in the design…

Random generation is always a complex task, and differences in results are usually very hard to debug. Besides, generation misbehavior always rings many bells in R&D :-)

A customer reported a random stability issue, explaining that the generator (IntelliGen) generated different values with the same seed. One simulation was started from vManager, the other in a Unix shell, and they ran in different run modes (compiled…

While a variety of EDA customer segments are growing, consumer electronics continues to drive the lion's share EDA of industry revenues.  Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business.  While I couldn't personally attend CES this year, like last year my two trusted agents (specifically, Unified Communications …

Starting with the Allegro PCB Editor 16.6 release, we can compare two constraint databases and view the constraint differences. This provides an efficient opportunity for designers to determine the differences between 2 designs.

Read on for more details

Generate a Constraint Difference Report

1. Open the Constraint Manager.
2. Select File > Import >  Constraints.
3. The 'Import Constraints' dialog box is displayed. Select…

One of the least-fun parts of running power and rail analysis has always been coming up with the electromigration (EM) model file. In the past, this involved cracking open the process design rule manual, finding the appropriate equations, and creating a spreadsheet to calculate all the numbers needed for the various metal width and via sizes. Then, this information had to be put in the format of the model file used by…

In addition to the R&D engineers who actually develop our software, the folks in many other groups here at Cadence put a lot of time and effort into creating a wide variety of documents, presentation and videos to help our users learn to use the software more effectively.  Today we're kicking off a new monthly series to highlight interesting and useful content recently added to the Cadence Online Support website in…

Designers need to radically re-think their strategies for timing closure to get the most out of process technologies that are becoming readily available. The additional burdens of creating electrical cell views for timing, power and signal integrity, accounting for process variability, managing leakage power, and hitting a low power budget make obtaining market leading performance extremely difficult.

To overcome these…

(defun sumlist_2b (numbers)
  (apply plus 0 0 numbers))

Unfortunately sumlist_2b cannot handle extremely long lists. In this posting, I will introduce sumlist_6 which does not suffer from this limitation.

This posting will not introduce any new SKILL++ primitives. Instead, it will use several primitives which have been…

Placement and routing have always been an integral part of printed circuit board design. The productivity of the product is often (if not always) achieved best if the PCB has a proper placement of the components and effective routing to support the placement. With the increased complexity of the designs and smaller board sizes, routing of signals has become more challenging. Designers are always looking for ways to ease…

Cadence holds a leading position in the EDA industry due to its broad product portfolio catering to digital and analog designs and the ever popular mixed-signal designs. With its immense technical and market leadership based on the Virtuoso platform for analog design and Encounter platform for digital design, Cadence EDA products helps designers achieve productivity gains and predictable design closure for today's complex…

Specman's Automatic GC Settings mechanism is aimed at eliminating the need for users to control the parameters which determine each Garbage Collection's behavior.

Setting config mem -automatic_gc_settings=STANDARD tells Specman to calculate all the parameters, to ensure that Specman's memory management system works in an optimal way.

The only parameter that is left for the user to play with is the -optimal…

Greetings,

Simulating crystal oscillators got a lot easier in MMSIM12.1...We have made enhancements to both Harmonic Balance and transient analyses.

In Part 1, I discussed Improvements to the Harmonic Balance use model.  With the new streamlined Choosing...

Greetings!

Simulating Crystal Oscillators got a lot easier in MMSIM12.1...We have made enhancments to both Harmonic Balance and Transient analyses.

In Part 1, I’ll cover Improvements to the Harmonic Balance use model. With a streamlined Choosing...