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In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application called Hosted Virtual Desktop, which supports increasingly mobile workers who want to use any smart, connected device to access corporate data resources.  Charles goes into detail about how Cadence IP can help expand the application to help businesses make mobile workforces more efficient.

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In my first blog of this quarterly series, I focused on how Rapid Adoption Kits (RAKs), developed by Cadence engineers, are enabling our users to be productive and proficient with Cadence products and technologies.  

In this second quarterly blog, let me explain the "Once Resolved, Reused Forever" internal process for documenting knowledge on https://support.cadence.com/. It ensures that we are not solving a problem…

Friends, you would probably agree that sharing knowledge is a practical way to solve business problems, and contributes to business goals. Thought I'd share some great content that I came across while navigating through https://support.cadence.com/

Rapid Adoption Kits:

Static Timing Analysis using Tempus (Signoff Timing Analysis) 13.2

With the help of this RAK (rapid adoption kit) you will learn how to perform static…

Over the past couple of years there has been some interest in applying a software development technique called unit testing in the hardware development flow. One of the reasons is that unit tests allow customers to validate their testbench in isolation, enabling very fast and thorough tests. Some customers have developed their own framework to accomplish this testing. In the Incisive 13.2 release, Cadence has introduced…

In this week's Whiteboard Wednesdays, Scott Jacobson completes his three-part series on the Memory Wall with a discussion on the different 3D memory solutions today and their market applications. You may recall that in the first segment, Scott examined how CPU performance outstrips memory transfers, and discussed options available to system designers, such as 2D solutions. In the second part of this series, Scott, took…

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. You can also compare the relative importance of the contributing instances.  The analysis results can aid in making…

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In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of new and updated mobile interfaces for mobile SoCs. These interfaces are broken down into three catagories—SoC fabric, memory, and chip-to-chip—and include ARM AMBA 4, ARM AMBA 5, OCP, DDR, LPDDR, LPDDR3, LPDDR4, Wide I/O, Wide I/O2, DRAM, eMMC, eMMC5, UFS, CSI-3, SoundWire, USB, PCIe, and SSIC.

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While there are several videos available for Allegro Design Entry HDL (DEHDL) in Cadence Online Support as well as in the product installation documentation folder ($CDSROOT/doc), there are times when a new specific video is produced for product features. Of course, there are many videos available for all the SPB products. Recently, several new videos have been produced for some of the more common functionality areas…

Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes.  However, redesign of circuitry is time-consuming, so it is common to migrate existing designs from previous projects, often from one process node to another.  Additionally, migration is also required for:

• Second sourcing on a similar process from a different foundry
• Reusing IP in next…

1. Only a single designer can work on the physical view of the design at one time
2. Multiple physical designers can work…

In this week's Whiteboard Wednesdays episode, Tom Hackett discusses why over 500 customers consider Cadence Verification IP to be the S.M.A.R.T. choice when looking to verify their SoC designs.

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In this week's Whiteboard Wednesdays installment, Cadence's Moshik Ruben takes a deeper look at the MIPI protocols that are the leading choice for certain mobile interfaces. Even though MIPI protocols are a top choice, however, they are being challenged by mobile versions of PCI Express and USB. Given this landscape, what does the future look like for MIPI and its challengers?  Watch this short video to find out…

The Virtuoso Analog Design Environment XL Monte Carlo sampling methods are Random, Latin Hypercube, and Low Discrepancy Sequence.  More accurately, Spectre provides the engine and ADE XL interfaces with the simulator to complete the Monte Carlo analysis task.  Random is the standard random sampling method.  Latin Hypercube (LHS) is an enhanced method that converges faster.  Low Discrepancy Sequence (LDS) is the most recently…

A design team at a customer of mine started out with Specman for the first time, having dabbled with a bit of SystemVerilog. I can't reveal any details of their design, but suffice to say they had a fun and not-so-simple challenge for me, the outcome of which I can share. Unlike some customers (and EDA vendors) who think it's a good test for a solver to do sudoku or the N-Queens puzzle (see this TeamSpecman blog…

Watch these demonstrations of RealTek's new ALC5677 audio codec - which uses HiFi EP running software from Sensory and ForteMedia.

http://youtu.be/VMPOhU_rYuM

In the above demo, Jason from RealTek shows how ForteMedia's iS620 noise processing software can be used for multi-microphone voice processing. iS620 dramatically improves the user experience in voice communication and voice recognition for smartphones.…

Time just got away from me last month, so here's two months worth of new content for your browsing enjoyment...

Videos

1. Integration Constraints Capability used in Mixed Signal Design Implementation

Explains and demonstrates the integration constraints capability of the Cadence Mixed-Signal Solution.

2. Virtuoso Floorplanning Design Flow Demo

Demonstrates the Virtuoso Floorplanner Flow: soft and hard blocks, defining cell…

In this week's Whiteboard Wednesdays episode, Scott Jacobson deep dives into 2D memory solutions like EMMC 5.0, UFS, and DDR4. Scott highlights how these solutions can help address CPU performance and power requirements and memory ability to deliver to these needs.


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MIPI protocols are expected to ship in over 4 billion mobile devices this year. That's billion with a "b".

Every year, new products are introduced at Mobile World Congress in Barcelona. Without MIPI interfaces, these products would not be able to perform nearly as well. You may not have heard about CSI-2, DSI, D-PHY, or many of the other MIPI standards, but thankfully there's the MIPI Alliance, a global…