Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Verification: Generic Dynamic Run-Time Operations with e Reflection, Part 1

teamspecman

Untyped Values and Value Holders
The reflection API in e not only allows you to perform static queries about your code, but it also allows you to perform dynamic operations on your environment at run time. For instance, you can use reflection to examine or modify the value of a field, or even invoke a method, in a generic way. This means that if the specific field or method name is unknown a priori, but you have the reflection…
- 5 Nov 2013
Analog/Custom Design: IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)

AndreasLenz

Virtuoso Space-Based Router (VSR) is routing solution integrated into the Virtuoso Layout Suite, which provides a comprehensive set of routing features for a variety of layout tasks. One major design task for layout designs is chip/block assembly routing in mixed-signal analog top (AoT) designs.

What's new in Virtuoso IC6.1.6?

VSR routing engines were enhanced to improve routing quality (QoR) and to give better…
- 29 Oct 2013
System, PCB, & Package Design : What's Good About DEHDL’s Variant Editor? 16.6 Has Several New Enhancements!

Jerry GenPart

The recent 16.6 QISR-2 for Allegro Design Entry HDL has new capabilities for the Variant Editor.

Read on for more details…

Dynamic Viewing of Variants in the Schematic Editor

A new toolbar and menus have been added for viewing variants:

All available variants for a design are listed. It’s easy to switch between any of the variants as well as base views. Selecting a variant will lead to the annotation of variant-specific…
- 29 Oct 2013
System, PCB, & Package Design : Turn Spreadsheet Ball Maps into Components in Seconds with 16.6 Cadence APD and SiP

Jeff Gallagher

Many designers use ball maps, or spreadsheets wherein each cell corresponds to a specific pin position in a regular pitch symbol, to document component interfaces, exchange data with other design teams, or even to optimize net assignments. But, just ...
- 24 Oct 2013
System, PCB, & Package Design : What's Good About Allegro PCB Editor ECSets and Ref Des Values? 16.6 Has a Few New Enhancements!

Jerry GenPart

Beginning with the 16.6 Allegro PCB Editor, the environment variable UPDATE_ECSET_REFDES is now the default behavior.

Read on for more details …

Most Electrical Constraint Sets (ECSets) will map based on Reference Designator (RefDes) values. It is sometimes the only thing that is unique for pins in a topology:

In this picture, U21 and U44 have the same SI model and the same pin use. So the only way to differentiate…
- 23 Oct 2013
System, PCB, & Package Design : What's Good About Allegro PCB Editor Embedded Net Name Display? Check Out 16.6!

Jerry GenPart

A new graphical display option in the 16.6 Allegro PCB Editor embeds net names within the cline path, pins, shapes, and flow lines. Useful in just about any PCB application, the display of net names will be extremely valuable for those involved in design reviews or board debug. This feature is enabled by default in all PCB products and does require Open GL to be enabled. The visibility controls for traces, pins, and shapes…
- 15 Oct 2013
System, PCB, & Package Design : Why Does Signal Integrity Analysis Need to be Power Aware?

TeamAllegro

Ever since the I/O Buffer Information Specification (IBIS) committee broke away from the "signal only" mentality and approved the new standard for including power information within the IBIS spec, there has been a lot of buzz in the industry about performing power-aware signal integrity analysis. Effectively this would mean combining both signal and power integrity analysis into one.

But why does it matter?…
- 11 Oct 2013
Verification: Starting Virtual Platform Simulation with Cadence Software Developer

jasona

Last time, I provided an introduction to the Eclipse setup for the Cadence Virtual System Platform. This time I will explain how to run simulation using Software Developer. Cadence Software Developer provides multiple flows to hand off...
- 11 Oct 2013
Analog/Custom Design: Virtuosity: 16 Things I Learned in September by Browsing Cadence Online Support

stacyw

Rapid Adoption Kits
By now, I think you know what RAKs are, and that they include a detailed instructional document and database. Use the title link above to access the main landing page and browse all the available material.
1. DRD-based Interactive Compactor
The DRD-based interactive compactor can help you change the spacing between existing objects in your layout either through compaction or spreading. It can also fix…
- 11 Oct 2013
Analog/Custom Design: SKILL for the Skilled: How to Shuffle a List

Team SKILL

The previous post of SKILL for the Skilled presented some ways to systematically visit all permutations of a list. As noted, the time to iterate through all permutations of a large list is prohibitive. If the goal is to find a permutation that meets some criteria then it may work perfectly well to simply test the criteria on randomly chosen permutations of the list and continue doing so until some time-out is reached…
- 9 Oct 2013
Verification: Combining the Linux Device Tree and Kernel Image for ARM

jasona

Back in 2010, I wrote two articles about a SystemC model used to load the Linux kernel and its various artifacts into memory for ARM virtual platforms. The first was A SystemC TLM 2.0 ARM Linux Boot Loader and the second was More on the SystemC ARM L...
- 8 Oct 2013
Verification: Getting Started with the Cadence Virtual System Platform: Software Developer

jasona

Cadence Software Developer is an exciting Eclipse-based product for developing, debugging, and analyzing embedded software. It has a long list of powerful capabilities that will make your job a lot easier - including transparent and intuitive one-cli...
- 8 Oct 2013
Verification: Trends in Using Software for System Verification

jasona

There is a clear trend to use more software running on the CPUs of a design for system verification. Historically, there has always been the pre-silicon operating system boot that was performed on emulators like Palladium. Typically, the boot was abo...
- 8 Oct 2013
Verification: e Macro Debugging

teamspecman

When creating a testbench using the MDV methodology, you want to write intelligent code whose behavior can be easily modified.
Using e macros can greatly improve your productivity by raising the level of abstraction at which these testbenches are created and used. With e macros, you can reduce the amount of code and simplify usage of code that needs to be used in several places in the testbench.
e macros are powerful code…
- 7 Oct 2013
Analog/Custom Design: Cadence’s Annual Mixed-Signal Summit 2013: A Mind Meld of Mixed-Signal Design Community

Sathish Bala

If you're a fan of the Star Trek series (my six-year-old son and I watch it together faithfully!), you know the Vulcan Mind Meld. (If you're not a Trekkie, the mind-meld is a process of transferring one's knowledge to another person instantly).

Mixed-Signal Technology Summit, Oct. 10 at Cadence's San Jose campus, is the closest thing to a mind meld to share mixed-signal design practices and challenges…
- 6 Oct 2013
System, PCB, & Package Design : What's Good About AMS Simulator IBIS Model Capability? It’s in the 16.6 Release!

Jerry GenPart
The 16.6 AMS Simulator now provides IBIS model simulation capability:

SPICE circuit generation for all IBIS versions
Support for V-T curves
Analog simulation of XNets (use Advanced Analysis tools for smoke analysis on bypass components)
Read on for more details …

The Model Editor now supports all versions of IBIS for V-T curves.

Invoke Modeled.exe.

Invoke the IBIS converter from the menu Model > IBIS Translator.

Browse…
- 6 Oct 2013
System, PCB, & Package Design : Take Notes During Your Packaging Design Workflow with the Database Diary

Jeff Gallagher

In this blog, we take a look, not at a new command, but instead at a classic command that many of you may not even realize is in the tool today: the database diary. The database diary tool (Tools -> Database Diary...) is available in all AP...
- 3 Oct 2013
Verification: Slow Winter or New Spring for Hardware Design?

Jack Erickson

If you're looking for an entertaining gonzo take on the history and current state of hardware design, I highly recommend "The Slow Winter" by James Mickens, the "Galactic Viceroy of Research Excellence" at Microsoft.The premis...
- 3 Oct 2013
System, PCB, & Package Design : What's Good About Capture’s Update Cache? 16.6 Has a Few Enhancements!

Jerry GenPart

The 16.6 OrCad Capture release now allows you to replace multiple cache parts in one operation. In addition, all options of Replace Cache now work on Update Cache.

Read on for more details…

In earlier releases, you could not use the options available under “Replace Cache” for “Update Cache” operations. You now have the option to select multiple parts in cache and replace them in one operation:…
- 3 Oct 2013
SoC and IP: TSMC 28HPM – Sweet Spot for Today’s Mobile SoCs

Jacek Duda

Mobile is the only business besides PCs where actual SoCs get a lot of visibility in the eyes of the end customer. Does Joe Doe care what’s inside his MP3 player or car infotainment system? No, not as long as it’s doing its job. But when it comes to his smartphone or a tablet, his awareness of the chip inside is much higher.
It’s good for the business, because this awareness helps IP providers promote…
- 2 Oct 2013
SoC and IP: Automotive Ethernet Interest Soars at Industry Events

ArthurM

I attended two consecutive automotive Ethernet events near Stuttgart last week. Judging by the level of participation automotive Ethernet is really taking off.
The first event was the OPEN Alliance face-to-face meeting which 150 people attended. The main purpose of the OPEN Alliance is to promote standards for the operation of 100M and 1G Ethernet PHYs over a single twisted pair (STP) of copper cable in automotive environments…
- 1 Oct 2013
System, PCB, & Package Design : Customer Support Recommended - Dimensioning in Allegro PCB Editor

Naveen

Allegro PCB Editor offers drafting and dimensioning features that support electronic design automation (EDA) industry standards that enable you to specify the dimensions of every feature on a board created from the product. This feature gives you greater control over the manufacturing release of your design. The layout editor also enables you to customize the dimensioning process to conform to the manufacturing requirements…
- 30 Sep 2013
System, PCB, & Package Design : What's Good About ADW’s Pull-Down Lists? 16.6 Has a Few New Enhancements!

Jerry GenPart

The 16.6 Allegro Design Workbench (ADW) release now provides the ability to customize the pull-down list values for part property editing. Some classification properties require “freeform” values (tolerance, voltage, etc.) and other properties only accept certain values, for example:
“YES/NO”
“COMPLIANT/NON-COMPLIANT”

This feature allows you to specify a set of allowable values for a property…
- 24 Sep 2013
SoC and IP: Intel Developer Forum (IDF13): A "Look Inside" the Technology Showcase

Arif Khan

The recent Intel Developer Forum 2013 in San Francisco was notable for the sheer number of attendees and the broad spectrum of the technology industry they represented.
Intel's embrace of a more diversified computing ecosystem was on display -- Android mascots, tablets, and phones, and yes, servers and cloud software. Intel led the PC revolution with its x86 family of processors, but faces intense competition in the handheld…
- 23 Sep 2013
SoC and IP: IEEE 802.3 -- Standardizing the Next Generation of Ethernet PHYs

ArthurM

I attended the IEEE 802.3 standards meeting in York, England recently. Over 200 people came from all over the world to work on standards for the next generation of Ethernet products.
Work is ongoing to standardize new Ethernet PHYs (physical layer devices) for speeds of 1Gbps, 40Gbps, 100Gbps and 400Gbps. The 1Gbps work is focused on the automotive and industrial market segments, a field that Cadence is particularly committed…
- 19 Sep 2013

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.