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Just a brief post this week to highlight one of the new SPB16.3 features in Allegro Design Entry CIS.

In complex designs containing a large number of parts, the task of wiring the parts together is often a time consuming and tedious task. Wiring multiple pins to a bus can also be a tedious and repetitive task. Capture now includes an Auto-Wiring feature that allows you to wire two or more pins or wires on your schematic…

Last week at DVCon, frequent Team Specman guest blogger Matan Vax of R&D gave a paper on "Where OOP Falls Short of Verification Needs".  In the following video, Matan elaborates on his paper, where it becomes clear that OOP languages like -- well, you know -- are at an inherent disadvantage vs. AOP approach (like in e) when it comes to the unique requirements of verification.

Click here if the embedded…

Boy, you must think we're a few sandwiches short of a picnic over here at Cadence.  

A couple of months ago we came out with this great new Virtuoso software release (IC 6.1.4).  So, despite my best efforts to get you to use the recently-opened files list or to create bookmarks, the first thing you did after starting virtuoso was open the Library Manager.  (Don't try to deny it, I know you did...). 

So there's the Library…

Click here or on the image below to go to the annotated photo blog of DVCon 2010 Day 3.

The images and notes include highlights from:

• A paper on "Where OOP Falls Short of Verification Needs" (And there is also a video interview of Matan elaborating on the paper

• The paper "Tweak Free Reuse With OVM"

• A paper on "Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoCs"…

I've spent much of this week at the San Jose Doubletree Hotel for DVCon 2010, and I have to say that it was a really good show. This is arguably the most important conference of the year for verification. DAC is lots bigger of course, but DVCon is really focused and there's a core group of colleagues and customers that always make it a fun and simulating event. Although DVCon is still officially the "Design & Verification…

Click here or on the image below to go to the annotated photo blog of DVCon Day 2.

Photos & notes include highlights from:

•  Brett Lammers' paper on "Apples to Apples HVL Comparison Finally Arrives"

• Lunch panel on "OVM found the bugs, now how do we debug them faster"

• Cadence CEO Lip-Bu Tan's keynote on "Breaking Through The Efficiency Barrier"

• Industry Leaders panel on…

This past weekend, several new enhancements and features were added to Cadence Online Support. I would encourage all customers to take a quick tour of these productivity enhancements. Below I've included some screenshots and examples of a few of these new and improved areas of Cadence Online Support.

Most of the new features you'll notice as soon as you login.

Email Notification is back, including an added notification…

A couple weeks ago, there was a good thread in the Digital Implementation Forums about managing buffering on nets between IOs and registers.  The post touched on a number of interesting topics, but one of the fundamental building blocks I'd like to expand upon in this blog entry is the fundamental task of writing to and reading from a file: File I/O.

It may seem like second nature for folks who use TCL-based tools like…

Click here or on the image below to go to the photo blog of DVCon Day 1.

While I've added descriptive captions to the images, allow me to address the FAQ: "How was the traffic on show floor?".  My unscientific observation was that the floor was a little lighter than last year, but this was a result of the tutorials being better attended and/or they "held" their audiences for longer.…

If you were looking for more evidence that the transition from RTL to ESL is gaining momentum, today at "Day 0" of DVCon (a/k/a "SystemC Day") you would discover plenty of supporting data points.  Here is a brief video interview with my colleague Steve Svoboda on the day's events, how far we've come from the first wave of SystemC hype back in 2000, and what Cadence is doing in this space:

The OVM SystemVerilog Class Library has built-in automation for many service routines that classes need for printing, copying, comparing and so on. OVM allows you to specify the automation needed for each field and to use a built-in, mature and consistent implementation of these routines. For each field you must use OVM field registration macros as in the example below:

     ...

     rand bit [15:0]           addr;

     rand…

Yeah, I know I'm a marketing guy but I really like this stuff!  For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation.  For all of the details, visit our DVCon events page.  Highlighted below are two of the items that I think will be of special interest.

Tutorial: OVM Advanced Topics

With UVM based on OVM, this is a must see…

This is a guest post from John McGehee.  John is an independent consultant in Silicon Valley, specializing in EDA application development and design.  He blogs about these topics at voom.net.  Prior to starting his consulting career, John was an AE at Avanti, Cadence Japan and Daisy Systems Japan.

In an earlier series of posts, I described techniques that will make your chip design flow easy to use. I subsequently had…

Just in time for DVCon 2010, I'm happy to inform you that revision 2 of the OVM e Scoreboard was just uploaded to OVMWorld: http://www.ovmworld.org

The main changes from rev1:

• A proper User Guide containing detailed descriptions and code examples for several popular use models 
• Performance improvements in the search algorithm

 
I encourage everyone who has already downloaded the original OVM e Scoreboard to download this…

There are plenty of new enhancements to the Allegro Design Workbench (ADW) solution in the ADW16.3 release.I'll be covering several of these over the coming weeks, but today's focus is the ADW Library Flow improvements.

A new bulk part release capability is available:

• Ability to pre-release/release multiple parts and models at the same time
• Prevents having to release each element individually
• Available directly from…

In case you or your management are wondering about Cadence's commitment to supporting the e language and/or Specman technology, allow us to direct your attention to this interview of Cadence Verification VP Mitch Weaver (who never worked for Verisity, BTW) by industry analyst Richard Goering.

As you'll see, with statements like, "Bottom line: cutting back on Specman/e would be like cutting our own throat"…

A couple of weeks ago, before going to bed one night I checked the statistics for the OVM World site. What I saw was really cool - exactly 10,000 registered users at the moment I looked! Being a social media guy these days, the first things I did was to tweet about it, and I was glad to see several re-tweets by OVM colleagues who also found this interesting and exciting.

My topic for today is another really cool thing…

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored activities is posted here).  Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language-related content, or be of general relevance to Specmaniacs.  Hence, if you are going to the event, please consider printing…

IBIS is sometimes known as the bird of knowledge, but is also the popular standard in modeling I/O buffers.  Well, IBIS recently grew some big new wings when the 5.0 version of the spec was ratified.  Those big wings include support for algorithmic modeling of SerDes transceivers.  Instead of just modeling with numbers and tables, the 5.0 standard now allows software modules or dynamically linked libraries (DLLs) to be included…

Allegro System Architect (ASA) also known as System Connectivity Manager (SCM) allows you to generate a schematic for your logical design. You can use the generated schematic for documentation purposes, or for communicating various aspects of the design to your team members or customers and for exporting it as an independent DEHDL design. Though the generated schematic is mainly for documentation purposes, for aesthetic…

The most common metrics used in current metric driven verification (MDV) flows are various forms of code coverage (block, FSM, toggle etc.), assertion coverage, and functional coverage.  As many of you know, all of these can be collected into Enterprise Manager for individual analysis, merged together into a single unified coverage score, and then ranked to easily identify the most effective elements of the testbench.