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Hello,

As a member of the technical committee and as the chair member for the Analog and Mixed-Signal Design and Verification track, I would like to invite you to submit an abstract to this conference.

We solicit papers for two types of sessions: technical papers and tutorials. Technical papers, which are up to 25 pages long, address design case studies and application overviews, and are presented in forty-minute sessions…

"Tackling formal assumptions through verification planning" is a recent article by Chris Komar and Frank Armbruster that is available on EDN. This article has fun with the old adage about what happens when you assume but very quickly get serious and applies it to functional verification and specifically formal property checking. It talks about potential problems of assumption escape and walks thought how this can…

The OVM provides the most comprehensive reuse if you follow the methodology it prescribes. While its unique built-in classes are the technical heart of the reuse, you still have to write your own components. Now you have the new Paradigm Works OVC Template Generator to write them in the right way for you.

Paradigm Works, an industry leader in functional verification services has helped clients verify complex chips…

People say I have strong google-fu.   Whether it's finding information on a homework topic for my kids or reviews for that little restaurant downtown, all it takes is a minute or two at the keyboard and there it is.  Searching for information has become a very important skill in today's world, both in "real life" and at work.  Laying your hands on reliable information quickly can make your life easier, amaze your…

In the course of performing design work in Encounter, it frequently becomes desireable to create a self-contained testcase that can be shared with colleagues at other sites, or with Cadence to aid in troubleshooting tool issues.  By self-contained, I mean the design data (netlist, floorplan, placement, routing, timing constraint files, etc) and all of the supporting collateral (.libs, LEFs, extraction tech files, etc…

Another design approach that Cadence supports that may not be obvious to all users…

The process of setting up a circuit simulation has historically been one of setting up all of the simulation control parameters (i.e. which analysis you want...

First - ABIML is an acronym for Algorithm-Based Interconnect Model Library.

Currently, the model in the interconnect model library (IML) can only be reused by matching model name, model type, or exact "TraceGeometryData", which includes key information such as shield layer, dielectric layer, trace layer and the exact trace physical geometry. If any of the model geometry data is mismatched, the field solver is called to…

[Please welcome Yuri Tsoglin of Specman R&D to the guest blogging rostrum.]

As my colleague Hilmar van der Kooij noted in a previous post, e's "defined as computed" macro capability is a great way to condense repetitive blocks of code into a few easy to read, parameterized lines. Building on Hilmar’s practical introduction, I’m going to ask you to take a step back and look at macros in broader context: specifically…

Some background info:
Taking a quick look at Power dissipation in CMOS:

Leakage power is well managed by powering down parts of the design when not in use. This is a well understood problem and can be simulated well in IUS (Incisive Unified Simulator) using CPF (Common Power Format) commands to capture power intent. For details refer to “A practical Guide to Low Power Design” – download a copy at …

Hello All,

Last week over in the LinkedIn Design Verification Professionals group, a thread came up in the discussion area regarding support for AOP in VERA.  The discussion quickly changed to the benefits of AOP for Verification.  Unfortunately, for the user who kicked off the thread, most of the other respondents seemed to only have experience with VERA's limited AOP capabilities and not with the more complete implementation…

Imagine this scenario: Your chip is a low power design. You’ve used everything in the book – clock gating, multiple threshold optimization, power shutoff, multiple supply voltages etc. What else can you do to reduce power in your design?

Or, maybe you can’t do power shutoff – the entire device is always on. Maybe you can’t use multiple supply voltages (face it – if you’re already running at 0.8V, how…

A few years ago I bought a wonderful book called "Earth From Above".  An amazing French photographer has put together a collection of truly unique aerial photographs of all kinds of unusual natural and man-made landscapes.  It's fascinating how different things look from high altitude--sometimes you can hardly recognize what you're looking at.  You wonder what that same scene would look like if you were…

Specmaniacs rejoice: there is a new blog centered around verification with e/Specman by Sandeep Gor:

http://digitalverification.blogspot.com/

Team Specman, and we dare say Specmaniacs everywhere, welcome this new resource to the community!

Here are some other e/Specman-oriented sites we know of, and by all means please send us links to any sites that are missing from this list so we can promote them:

* The venerable Specman…

Earlier today at the Cadence San Jose campus, a charity event was held off-cycle from the regular "Stars & Strikes" charity event series, where this time the focus was on food with a hot dog eating contest to benefit for Second Harvest Food Bank’s "Share Your Lunch Drive".

For more images from the event, click here for an annotated gallery

This event might seem like it's coming…

For EDA software, it seems that it takes just as much effort to develop a methodology to use the software, as writing the tool itself. Ask any CAD group or design group that has to develop their own methodology and you can quickly gauge the many challenges in building a flow for your favorite EDA tool.

Why is it so hard to build and maintain a working flow? There are many reasons. First of all, EDA tools change.…

I read a recent article (June 11, 2009) in EDN magazine - "USB 3.0: A simple Idea Full of Challenges" by Ron Wilson.

In a nutshell, Ron says "Super-speed USB (Universal Serial Bus) 3.0 sounds like a great idea. Just start with widely used, fast, and bulletproof USB 2.0 and graft in the PHY (physical-layer) interface from another common and reliable standard, PCIe (peripheral-component-interconnect…