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Breakfast Bytes: Spectre and Meltdown: An Update

Paul McLellan

I wrote an extra Breakfast Bytes post a couple of weeks ago about Spectre and Meltdown, which had suddenly become public a week earler than apparently was planned (having been disclosed to the relevant companies months before). I wrote that post only...
- 17 Jan 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Verification Challenges for SoCs Integrating PCI Express Subsystem IP

References4U

In this week's Whiteboard Wednesdays video, Nick Heaton, Distinguished Engineer, Cadence, describes the verification challenges for SoCs when integrating PCI Express subsystem IP.

www.youtube.com/watch
- 16 Jan 2018
Analog/Custom Design: Virtuosity and Virtuoso Video Diary: Onwards and Upwards

Ashu V

Looking back at 2017, I note with satisfaction that it was a phenomenal year of blogging that saw us achieving tons more than we’d dreamed of. Our twin series of blog posts—Virtuosity and the Virtuoso Video Diary—garnered appreciation from all around the world and made it to that coveted special zone in the web browser of our readers—Favorites! Beginning small sometime in the middle of 2016, these series now attract a…
- 16 Jan 2018
Breakfast Bytes: IEDM Short Course: After 5nm

Paul McLellan

The Sunday of IEDM is always two full-day short courses. One is on the future of memory technology, one is on the future of logic technology. This year the logic one was titled Boosting Performance, Ensuring Reliability, Managing Variation in Sub-5nm...
- 16 Jan 2018
Verification: This Was 2017, Looking Forward 2018

teamspecman

With 2017 just out of the door, this is a good time to stop for a few minutes, look back at 2017, and plan ahead for 2018 and the years to come.

While thinking of the projects and challenges awaiting you, don’t miss this video - Specman news, Jan 2018 - an interview with Orit Kirshenberg, the manager of Specman R&D.

In this interview, Kirshenberg shares her view of Specman evolution in 2017, and some of the…
- 16 Jan 2018
Breakfast Bytes: Mobile World Congress in One Keynote

Paul McLellan

It was CES last week. Generally, this is not an event about mobile, mainly because the big show for that industry is Mobile World Congress (MWC), which takes place in Barcelona a month or so later. For the last couple of years, I have attended and wr...
- 15 Jan 2018
Breakfast Bytes: CES Keynotes: Cars, Flying Cars, Dancers, Music, Lights...and Sustainability

Paul McLellan

As I said yesterday, it was the Consumer Electronics Show this week. I attended the two big keynotes. The opening keynote on Monday night is traditionally Brian Krzanich of Intel. The next morning, the day the show really opens (the exhibit floo...
- 12 Jan 2018
Verification: CRAFTing Your Aero/Defense UVM Testbench the Easy Way

XTeam

So you want to build an automated testbench for your aero/defense project, eh? Luckily, there’s a solution for you. A project called CRAFT (which stands for Circuit Realization At Faster Timescales) seeks to speed the development of SoCs by providing the tools necessary to make automated testbenches faster and more easily created than ever before.

Funded by DARPA, CRAFT utilizes components from a number of different…
- 11 Jan 2018
Breakfast Bytes: CES Review: Rain...and Some Consumer Electronics

Paul McLellan

I have been at the Consumer Electronics Show (CES) all week. For 116 days through the winter so far, there has been no rain at all in Las Vegas. But once 170,000 attendees came to town, the heavens opened. Getting between the halls became more of a c...
- 11 Jan 2018
System, PCB, & Package Design : SI Methodology for Multi-Gigabit Serial Link Interfaces (5 of 8)

Sigrity

Efficient Interconnect Extraction Once physical layout is complete, (or at least the serial link differential pairs of interest are routed), post-layout verification can take place. One decision to make is to decide what bandwidth to use for the extr...
- 11 Jan 2018
Breakfast Bytes: What's For Breakfast? Video Preview January 15th to 19th 2018

Paul McLellan

https://youtu.be/MPkAPCQyFvY Coming from Consumer Electronics Show, Las Vegas (camera me) Monday: 5G Keynote Panel Tuesday: IEDM Post-5nm Short Course Wednesday: Update on Spectre and Meltdown Thursday: Ken Thompson's Turing Award...
- 10 Jan 2018
Verification: User Extensions to DUT Error

teamspecman

A question was raised to stackoverflow about how can one extend the dut_error() for printing more information. The capability to provide the test runners and debuggers more information upon an error can be a great enhancement to the quality and usability of the verification environment, so I decided to extend here a bit the answer given in the stackoverflow.

The request was worded: Can we extend the dut_error() method to print…
- 10 Jan 2018
Verification: App Note Spotlight - Introduction to Connect Modules

XTeam

Welcome to the App Note Spotlight—a bi-weekly series where the XTeam highlights an app note that contains valuable information you may not be aware of. Today, we're going to look at connect modules—what they are, and why you should care about them.

A Quick Run-Down on Connect Modules

To understand connect modules, we'll need to step back a bit. First, understand that mixed-signal simulation has to happen…
- 10 Jan 2018
Breakfast Bytes: Post-Silicon Compute

Paul McLellan

At the SEMI Strategic Materials Conference (SMC) a few weeks ago, Lucian Shifren of Arm Research talked about Post Silicon Compute. I always like presentations by Arm Research on semiconductor stuff. Since they don't have their own process, or th...
- 10 Jan 2018
The India Circuit: Exciting Trends in 2018: An Interview with Jaswinder Ahuja

Madhavi Rao

Jaswinder Ahuja is well-known to everyone in the semiconductor and electronics industry in India. He has been Cadence India’s Managing Director since 1996, and is one of the handful of employees WW who will be completing 30 years with Cadence. ...
- 9 Jan 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - What to expect from TLM 2.0 Models for Memory Subsystems - Part 2

References4U

In this week's Whiteboard Wednesday, Vivek Nandakumar continues his explanation of the behavioral differences between Loosely Timed (LT) and Approximately Timed (AT) TLM 2.0 models.

www.youtube.com/watch
- 9 Jan 2018
Breakfast Bytes: Virtuoso System Design Platform Is Product of the Year

Paul McLellan

The title of this post says it all, but I'd better add a bit of color. Cadence was honored with an Electronic Products' Product of the Year award for the Virtuoso System Design Platform. This is the 42nd year that Electronic Products has...
- 9 Jan 2018
Breakfast Bytes: 2017: A Year in Breakfasts

Paul McLellan

So 2017 is over. Taylor Swift got into trouble for saying it was a great year and not being political enough. Well, I hope that I'm not going to get into trouble for saying 2017 was a great year for the whole semiconductor ecosystem (and Breakfas...
- 8 Jan 2018
Verification: Portable Stimulus User Gives Perspec PSS Technology Nearly Perfect Review

Steve Brown

It’s always good to hear what real users think of products. Here is a very detailed review (~4000 words) by an Anonymous user, nick named Ant-Man (from the movie). Overall it’s a very strong endorsement of Perspec, and summarize...
- 8 Jan 2018
Verification: Register for the UVM Register Layer Webinar on January 12!

XTeam

On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim of helping users model UVM in certain less-intuitive ways. This webinar will cover the usage of user-defined front and back doors to extend register-layer capabilities past simple call-and-response transactions, understanding the role the predictor plays in updating the register model, and how to use register callbacks to model strange…
- 5 Jan 2018
Breakfast Bytes: GLOBALFOUNDRIES 7nm

Paul McLellan

Earlier in the week, I wrote about my meeting with Gary Patton the day before GLOBALFOUNDRIES presented their 7nm process as IEDM. See Gary Patton on GF, IBM, 7nm, EUV, and More for more details. Earlier in the morning, Intel had announced detai...
- 5 Jan 2018
Analog/Custom Design: Automatically Reusing an SoC Testbench in AMS IP Verification

msteam

The complexity and size of mixed-signal designs in wireless, power management, automotive, and other fast growing applications requires continued advancements in a mixed-signal verification methodology. An SoC, in these fast growing applications, incorporates a large number of analog and mixed-signal (AMS) blocks/IPs, some acquired from IP providers, some designed, often concurrently. AMS IP must be verified independently…
- 4 Jan 2018
System, PCB, & Package Design : SI Methodology for Multi-Gigabit Serial Link Interfaces (4 of 8)

Sigrity

Enabling Constraint-Driven Design With the pre-layout testbench built, populated with relevant models, and producing realistic simulation results, it is time to get constraints in place to drive and control the physical layout of the serial link. Thi...
- 4 Jan 2018
Breakfast Bytes: CES18 Preview

Paul McLellan

It's the start of a new year and that means it is the Consumer Electronics Show in Las Vegas. Although it is a zoo, it is a good place to get a feel for what is new in the consumer electronics space (and that increasingly includes automotive, not...
- 4 Jan 2018
Breakfast Bytes: What is Meltdown? How Can It Affect Both Intel and Arm?

Paul McLellan

If you pay attention to anything to do with processors, security, or even investment discussion sites covering companies like Intel, you may be aware that 2018 has started with the discovery of a major security flaw that affects all high-end micropro...
- 3 Jan 2018

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