Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Analog/Custom Design: Virtuosity: CDNLive India—Our Window to KYC!

Rishu Misri Jaggi

In line with the recently-implemented mandate in India requiring banks and financial institutions to regularly run “Know Your Customer (KYC)” cycles, CDNLive India has become a reliable event for the Technical Communications Engineering team to regularly touch base with customers, and to ensure the team knows their customers in order to exceed customer expectations.

The Publications Infrastructure and CPG…
- 4 Dec 2017
Breakfast Bytes: What's For Breakfast? Video Preview December 11th to 15th 2017

Paul McLellan

https://youtu.be/Ar98HS9Dnow Coming from Union Square, San Francisco (camera Carey Guo) Monday: COTS: Standard Products in US Government Electronics Tuesday: RISC-V Workshop, Milpitas Wednesday: Ploughing 1 TB of RAM with Twenty x86 Oxen a...
- 4 Dec 2017
SoC and IP: Book Your CES Meetings Now!

PaulaJones

Want to see the exciting technology that is behind some of the biggest innovations at CES? Book a meeting now to visit the Cadence invitation-only suites at CES 2018, January 9-12, South Hall 2, Suite MP2577 (same location as last year). See Tensilic...
- 4 Dec 2017
Breakfast Bytes: Formal Verification Sign-Off...and the First Text Message

Paul McLellan

Recently, it was the 10th annual Jasper User Group meeting (see my earlier post Jasper User Group 2017 for more background and a summary of the two best papers presented, at least as judged by the audience). There were also two invited pape...
- 4 Dec 2017
RF Engineering: How to Set Up and Plot Large-Signal S Parameters?

KamalKishore

Large-signal S-parameters (LSSPs) are an extension of small-signal S-parameters and are defined as the ratio of reflected (or transmitted) waves to incident waves.
- 4 Dec 2017
Verification: Perspec System Verifier is #1 in Portable Stimulus in 2017 User Survey

Steve Brown

It’s now official: Perspec System Verifier is rated the #1 product in the #1 category of Portable Stimulus, according to the 2017 EDA User Survey published on Deepchip.com. There were 33 user responses in favor of Perspec as the #1 tool, and dr...
- 1 Dec 2017
Breakfast Bytes: Silexica: Mastering Multicore

Paul McLellan

Since the invention of the microprocessor, it was a dream that it would be possible to build a really powerful computer by taking a lot of cheap simple computers and putting them together. This was especially a dream of hardware designers, who could ...
- 1 Dec 2017
Breakfast Bytes: Jasper User Group: How to Be a Formal Verification Lead

Paul McLellan

Recently, it was the 10th annual Jasper User Group meeting (see my earlier post Jasper User Group 2017 for more background, and a summary of the two "best" papers presented). There were also two invited papers. To open the first day, t...
- 30 Nov 2017
RF Engineering: Triple Beat Analysis: What, Why & How?

kmayank

The Triple Beat analysis is similar to Rapid IP2/IP3 analysis except that it uses three tones instead of two. It is used in cases where two closely-spaced small-signal inputs from a transmitter leak in to the receiver along with an intended small-signal RF input signal.
- 30 Nov 2017
The India Circuit: Hello, My Name Is Anna. Can I Help You?

Madhavi Rao

Chatbots are annoyingly familiar to anyone who has shopped online. The distracting little box on the bottom right of your screen saying chirpily, “Hello! My name is Anna. Can I help you?”. What I find most irritating is the fact that they...
- 29 Nov 2017
Verification: Check Again: Cadence Announces Release of the First PCIe 5.0 VIP—With TripleCheck!

XTeam

On November 28, 2017, Cadence announced the release of the first available PCIe® 5.0 Verification IP. This new VIP gives designers access to Cadence’s TripleCheck technology—which gives designers a comprehensive verification plan that uses measurable objectives related to spec features, along with a test suite containing thousands of tests. These combine to greatly improve the speed and quality of functional…
- 29 Nov 2017
Breakfast Bytes: Chips and Technologies: The First Fabless Company

Paul McLellan

As part of writing Fabless: the Transformation of the Semiconductor Industry a couple of years ago, I wanted to cover Chips and Technologies, which I believed was the first fabless semiconductor company. One of the founders was Dadao Banatao, no...
- 29 Nov 2017
Breakfast Bytes: November Breakfast Buffet

Paul McLellan

https://youtu.be/paqvuLll4pM Coming from the rain on the roof of Cadence building 10 (camera Sean) Rob Rutenbar Is Recipient of 2017 Kaufman Award Social Engineering Jasper User Group 2017 The Alto—Forty Years On Chips and Technologies: The Fi...
- 29 Nov 2017
Whiteboard Wednesdays: Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 1

References4U

In this week's Whiteboard Wednesday, Tom Hackett explains neural network basics using an Excel spreadsheet as a learning vehicle. You can download the spreadsheet here: https://ip.cadence.com/uploads/1213/neural-network-calculator-xlxs-zip

www.youtube.com/watch
- 28 Nov 2017
Breakfast Bytes: CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper

Paul McLellan

CCIX (pronounced see-six) is the Cache Coherent Interconnect for Accelerators. I wrote about it in my post CCIX is Pronounced C6 and also when Cadence announced its collaboration with TSMC, Arm and Xilinx in Xilinx/Arm/Cadence/TSMC Announce Worl...
- 28 Nov 2017
RF Engineering: Measuring Rapid IP3

Jommy

In the world of analog design, IP3—the third order intercept point, is a known parameter that is used to measure the linearity in the radio frequency (RF) components. The extracted IP3 values are very essential to determine the operating power ...
- 27 Nov 2017
Breakfast Bytes: What's For Breakfast? Video Preview December 4th to 8th 2017

Paul McLellan

https://youtu.be/LcmP8GkqvEw Coming from outside on the Cadence campus (camera Sean) Monday: JUG: Formal Verification Signoff Tuesday: Supercomputers Wednesday: Advanced Packaging Delivers More than Moore Thursday: Greg Yeri...
- 27 Nov 2017
Breakfast Bytes: What's the Difference Between MOESI and MESI? Cache-Coherence for Poets

Paul McLellan

Increasingly, a lot of SOCs contain multicore processors, multiple separate processors, accelerators, and high-performance DMA devices. They also have cache memories, memories local to a block or core, used to improve performance. This causes a big p...
- 27 Nov 2017
Digital Design: Cadence Modus DFT at International Test Conference 2017

Rob Knoth

While DAC is the focal point for the EDA industry, the test community travels in a slightly separate orbit. There are many conferences throughout the year, and around the globe, to help bridge the problems and solutions in academia and the industry....
- 22 Nov 2017
Verification: 26262 4U: Infineon and the Incisive Functional Safety Simulator

XTeam

Infineon and Cadence have a bit of a history: they’ve been working together on functional safety mechanisms for around two and a half years now, and Infineon has been using the entire Cadence verification suite since the nineties. Functional safety is a serious hurdle for the automotive industry, and with the rise of ADAS systems, the issues that face Cadence and Infineon are about to get a lot more complicated…
- 22 Nov 2017
Breakfast Bytes: What You See Isn't Always What You Get

Paul McLellan

I wrote earlier in the week, in my post The Alto—Forty Years On, about the origin of the term WYSIWYG (pronounced whizzy-wig if you didn't already know). Today, it's the day before a break so I traditionally write about something completely off...
- 22 Nov 2017
System, PCB, & Package Design : A Peek into the Future of Signal Integrity with Artificial Neural Networks

Sigrity

Imagine how great life could be if computers or robots can do all our tedious work and we get to enjoy life and work on the things that are meaningful to us, i.e. the first figure on our left. These aspirations are definitely the goals of many ...
- 21 Nov 2017
The India Circuit: Will Artificial Intelligence Take Over Art Forms?

Madhavi Rao

In February last year, San Francisco’s art lovers were treated to a new kind of exhibition. Titled, “DeepDream: The Art of Neural Networks” and held in the trendy Mission District, the art on display was otherworldly, strange, and p...
- 21 Nov 2017
Analog/Custom Design: Virtuosity: Organizing Waveform Families

Arja H

When plotting waveforms in Virtuoso Visualization and Analysis across sweeps you might want to group plots with the same values together, or display each corner in the same color etc. Of course, you can right-click on the plot and select Copy to or Move to and move the plots manually, but did you know there was an assistant to do this for you?
- 21 Nov 2017
Breakfast Bytes: The Alto—Forty Years On

Paul McLellan

I talked yesterday about the history of the Xerox PARC Alto machine, which is a computer from the 1970s that is still influencing your smartphone today. On December 10th, forty years to the day after the presentation of the Alto to Xerox management a...
- 21 Nov 2017

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.